[llvm-commits] PATCH: Tailcallopt x86 byval argument handling

[Arnold Schwaighofer]

On Fri, Apr 11, 2008 at 2:10 AM, Evan Cheng <evan.cheng at apple.com> wrote:
>  Thanks. The patch looks good. Have you verified the register allocator
>  does eliminate the unnecessary copies?
Depends on what your notion of verify is. I checked with a few examples. :)

The copying of arguments for register parameters to virtual registers
and back to the parameter's register  is only emitted in cases where
tail call opt is on and the function call contains a byval argument.
So tail calls without byval arguments would not pay the price. So even
in this case i wouldn't be so bad?

take for example the following call:

define  fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) {
entry:
        %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
        %tmp3 = load i64* %tmp2, align 8
        %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* %a byval,
i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
        ret i64 %tmp4
}

as you can see 3rd (7) and 5th (17) argument are directly moved to
their corresponding argument register (rdx,r8). only rsi, rdi, rcx are
moved to intermediate registers as expected (killed by byval
lowering). as note that when i say 3rd i really mean 4th (b) but since
the first argument is byval and passed on the stack it i do not take
into account. so it seems the allocator is doing it's job nicely.

tailcaller:
	pushq	%rbx
	subq	$32, %rsp
	movq	%rdi, %rax
	movq	56(%rsp), %r9
	movl	$6, %r10d
	leaq	48(%rsp), %rsi
	movq	%r10, %rcx
	movq	%rsp, %rdi
	rep;movsl
	leaq	48(%rsp), %rdi
	movl	$13, %ebx
	movl	$7, %edx
	movl	$17, %r8d
	movq	%r10, %rcx
	movq	%rsp, %rsi
	rep;movsl
	movq	%r9, %rdi
	movq	%rax, %rsi
	movq	%rbx, %rcx
	addq	$32, %rsp
	popq	%rbx
	jmp	tailcallee  # TAILCALL
	.size	tailcaller, .-tailcaller

okay to commit?