[llvm-commits] [llvm] r49166 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveIntervalAnalysis.cpp
Evan Cheng
evan.cheng at apple.com
Thu Apr 3 09:39:43 PDT 2008
Author: evancheng
Date: Thu Apr 3 11:39:43 2008
New Revision: 49166
URL: http://llvm.org/viewvc/llvm-project?rev=49166&view=rev
Log:
- Treat a live range defined by an implicit_def as a zero-sized one.
- Eliminate an implicit_def when it's being spilled.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=49166&r1=49165&r2=49166&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Thu Apr 3 11:39:43 2008
@@ -394,6 +394,10 @@
BitVector &RestoreMBBs,
std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes);
+ /// removeSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
+ /// spilled.
+ void removeSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm);
+
/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
/// interval on to-be re-materialized operands of MI) with new register.
void rewriteImplicitOps(const LiveInterval &li,
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=49166&r1=49165&r2=49166&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Apr 3 11:39:43 2008
@@ -201,6 +201,11 @@
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
+ if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ DOUT << "is a implicit_def\n";
+ return;
+ }
+
// Virtual registers may be defined multiple times (due to phi
// elimination and 2-addr elimination). Much of what we do only has to be
// done once for the vreg. We use an empty interval to detect the first
@@ -1105,7 +1110,7 @@
std::vector<RewriteInfo> RewriteMIs;
for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
re = mri_->reg_end(); ri != re; ) {
- MachineInstr *MI = &(*ri);
+ MachineInstr *MI = &*ri;
MachineOperand &O = ri.getOperand();
++ri;
assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
@@ -1307,6 +1312,22 @@
Restores[i].index = -1;
}
+/// removeSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
+/// spilled.
+void LiveIntervals::removeSpilledImpDefs(const LiveInterval &li,
+ VirtRegMap &vrm) {
+ for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
+ re = mri_->reg_end(); ri != re; ) {
+ MachineInstr *MI = &*ri;
+ ++ri;
+ if (MI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
+ continue;
+ RemoveMachineInstrFromMaps(MI);
+ vrm.RemoveMachineInstrFromMaps(MI);
+ MI->eraseFromParent();
+ }
+}
+
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li,
@@ -1386,6 +1407,8 @@
}
IsFirstRange = false;
}
+
+ removeSpilledImpDefs(li, vrm);
return NewLIs;
}
@@ -1454,8 +1477,10 @@
}
// Insert spills / restores if we are splitting.
- if (!TrySplit)
+ if (!TrySplit) {
+ removeSpilledImpDefs(li, vrm);
return NewLIs;
+ }
SmallPtrSet<LiveInterval*, 4> AddedKill;
SmallVector<unsigned, 2> Ops;
@@ -1608,6 +1633,7 @@
}
}
+ removeSpilledImpDefs(li, vrm);
return RetNewLIs;
}
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