[llvm-commits] [llvm] r48855 - in /llvm/trunk/lib/Target/X86: X86Instr64bit.td X86InstrInfo.cpp X86InstrInfo.td

[Evan Cheng]

Author: evancheng
Date: Wed Mar 26 20:41:09 2008
New Revision: 48855

URL: http://llvm.org/viewvc/llvm-project?rev=48855&view=rev
Log:
Allow certain lea instructions to be rematerialized.

Modified:
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=48855&r1=48854&r2=48855&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Mar 26 20:41:09 2008
@@ -154,6 +154,7 @@
                   "lea{l}\t{$src|$dst}, {$dst|$src}",
                   [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
 
+let isReMaterializable = 1 in
 def LEA64r   : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
                   "lea{q}\t{$src|$dst}, {$dst|$src}",
                   [(set GR64:$dst, lea64addr:$src)]>;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=48855&r1=48854&r2=48855&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Mar 26 20:41:09 2008
@@ -734,46 +734,77 @@
 }
 
 
+ static bool regIsPICBase(MachineInstr *MI, unsigned BaseReg) {
+   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
+   bool isPICBase = false;
+   for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
+          E = MRI.def_end(); I != E; ++I) {
+     MachineInstr *DefMI = I.getOperand().getParent();
+     if (DefMI->getOpcode() != X86::MOVPC32r)
+       return false;
+     assert(!isPICBase && "More than one PIC base?");
+     isPICBase = true;
+   }
+   return isPICBase;
+ }
+ 
 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
   switch (MI->getOpcode()) {
   default: break;
-  case X86::MOV8rm:
-  case X86::MOV16rm:
-  case X86::MOV16_rm:
-  case X86::MOV32rm:
-  case X86::MOV32_rm:
-  case X86::MOV64rm:
-  case X86::LD_Fp64m:
-  case X86::MOVSSrm:
-  case X86::MOVSDrm:
-  case X86::MOVAPSrm:
-  case X86::MOVAPDrm:
-  case X86::MMX_MOVD64rm:
-  case X86::MMX_MOVQ64rm:
-    // Loads from constant pools are trivially rematerializable.
-    if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
-        MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
-        MI->getOperand(2).getImm() == 1 &&
-        MI->getOperand(3).getReg() == 0) {
-      unsigned BaseReg = MI->getOperand(1).getReg();
-      if (BaseReg == 0)
-        return true;
-      // Allow re-materialization of PIC load.
-      MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
-      bool isPICBase = false;
-      for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
-             E = MRI.def_end(); I != E; ++I) {
-        MachineInstr *DefMI = I.getOperand().getParent();
-        if (DefMI->getOpcode() != X86::MOVPC32r)
-          return false;
-        assert(!isPICBase && "More than one PIC base?");
-        isPICBase = true;
-      }
-      return isPICBase;
+    case X86::MOV8rm:
+    case X86::MOV16rm:
+    case X86::MOV16_rm:
+    case X86::MOV32rm:
+    case X86::MOV32_rm:
+    case X86::MOV64rm:
+    case X86::LD_Fp64m:
+    case X86::MOVSSrm:
+    case X86::MOVSDrm:
+    case X86::MOVAPSrm:
+    case X86::MOVAPDrm:
+    case X86::MMX_MOVD64rm:
+    case X86::MMX_MOVQ64rm: {
+      // Loads from constant pools are trivially rematerializable.
+      if (MI->getOperand(1).isReg() &&
+          MI->getOperand(2).isImm() &&
+          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
+          MI->getOperand(4).isCPI()) {
+        unsigned BaseReg = MI->getOperand(1).getReg();
+        if (BaseReg == 0)
+          return true;
+        // Allow re-materialization of PIC load.
+        MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
+        bool isPICBase = false;
+        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
+               E = MRI.def_end(); I != E; ++I) {
+          MachineInstr *DefMI = I.getOperand().getParent();
+          if (DefMI->getOpcode() != X86::MOVPC32r)
+            return false;
+          assert(!isPICBase && "More than one PIC base?");
+          isPICBase = true;
+        }
+        return isPICBase;
+      } 
+      return false;
     }
-      
-    return false;
+ 
+     case X86::LEA32r:
+     case X86::LEA64r: {
+       if (MI->getOperand(1).isReg() &&
+           MI->getOperand(2).isImm() &&
+           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
+           !MI->getOperand(4).isReg()) {
+         // lea fi#, lea GV, etc. are all rematerializable.
+         unsigned BaseReg = MI->getOperand(1).getReg();
+         if (BaseReg == 0)
+           return true;
+         // Allow re-materialization of lea PICBase + x.
+         return regIsPICBase(MI, BaseReg);
+       }
+       return false;
+     }
   }
+
   // All other instructions marked M_REMATERIALIZABLE are always trivially
   // rematerializable.
   return true;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=48855&r1=48854&r2=48855&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Mar 26 20:41:09 2008
@@ -464,6 +464,7 @@
 def LEA16r   : I<0x8D, MRMSrcMem,
                  (outs GR16:$dst), (ins i32mem:$src),
                  "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
+let isReMaterializable = 1 in
 def LEA32r   : I<0x8D, MRMSrcMem,
                  (outs GR32:$dst), (ins lea32mem:$src),
                  "lea{l}\t{$src|$dst}, {$dst|$src}",