[llvm-commits] [llvm] r48577 - in /llvm/trunk: lib/CodeGen/MachineInstr.cpp lib/CodeGen/PrologEpilogInserter.cpp lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.cpp utils/TableGen/CodeGenDAGPatterns.cpp
Chris Lattner
sabre at nondot.org
Wed Mar 19 18:22:40 PDT 2008
Author: lattner
Date: Wed Mar 19 20:22:40 2008
New Revision: 48577
URL: http://llvm.org/viewvc/llvm-project?rev=48577&view=rev
Log:
detabify llvm, patch by Mike Stump!
Modified:
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Mar 19 20:22:40 2008
@@ -738,7 +738,7 @@
if (!Reg || IncomingReg == Reg ||
!TargetRegisterInfo::isPhysicalRegister(Reg) ||
!TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
- ++i;
+ ++i;
continue;
}
@@ -748,17 +748,17 @@
return true;
if (RegInfo->isSubRegister(IncomingReg, Reg) && MO.isKill()) {
- if (MO.isImplicit()) {
- // Remove this implicit use that marks the sub-register
- // "kill". Let the super-register take care of this
- // information.
- RemoveOperand(i);
- --e;
- continue;
- } else {
- // The super-register is going to take care of this kill
- // information.
- MO.setIsKill(false);
+ if (MO.isImplicit()) {
+ // Remove this implicit use that marks the sub-register
+ // "kill". Let the super-register take care of this
+ // information.
+ RemoveOperand(i);
+ --e;
+ continue;
+ } else {
+ // The super-register is going to take care of this kill
+ // information.
+ MO.setIsKill(false);
}
}
}
@@ -781,9 +781,9 @@
}
if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
- TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isKill())
+ TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ RegInfo->isSuperRegister(IncomingReg, Reg) &&
+ MO.isKill())
// A super-register kill already exists.
return true;
}
Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Mar 19 20:22:40 2008
@@ -520,57 +520,57 @@
if (I->getOpcode() == TargetInstrInfo::DECLARE) {
// Ignore it.
++I;
- continue;
+ continue;
}
if (I->getOpcode() == FrameSetupOpcode ||
I->getOpcode() == FrameDestroyOpcode) {
// Remember how much SP has been adjusted to create the call
// frame.
- int Size = I->getOperand(0).getImm();
+ int Size = I->getOperand(0).getImm();
- if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
- (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
- Size = -Size;
+ if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
+ (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
+ Size = -Size;
- SPAdj += Size;
+ SPAdj += Size;
- MachineBasicBlock::iterator PrevI = prior(I);
- TRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
+ MachineBasicBlock::iterator PrevI = prior(I);
+ TRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
- // Visit the instructions created by eliminateCallFramePseudoInstr().
- I = next(PrevI);
- continue;
+ // Visit the instructions created by eliminateCallFramePseudoInstr().
+ I = next(PrevI);
+ continue;
}
bool DoIncr = true;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isFrameIndex()) {
- // Some instructions (e.g. inline asm instructions) can have
- // multiple frame indices and/or cause eliminateFrameIndex
- // to insert more than one instruction. We need the register
- // scavenger to go through all of these instructions so that
- // it can update its register information. We keep the
- // iterator at the point before insertion so that we can
- // revisit them in full.
- bool AtBeginning = (I == BB->begin());
- if (!AtBeginning) --I;
-
- // If this instruction has a FrameIndex operand, we need to
- // use that target machine register info object to eliminate
- // it.
- TRI.eliminateFrameIndex(MI, SPAdj, RS);
-
- // Reset the iterator if we were at the beginning of the BB.
- if (AtBeginning) {
- I = BB->begin();
- DoIncr = false;
- }
-
- MI = 0;
- break;
- }
+ if (MI->getOperand(i).isFrameIndex()) {
+ // Some instructions (e.g. inline asm instructions) can have
+ // multiple frame indices and/or cause eliminateFrameIndex
+ // to insert more than one instruction. We need the register
+ // scavenger to go through all of these instructions so that
+ // it can update its register information. We keep the
+ // iterator at the point before insertion so that we can
+ // revisit them in full.
+ bool AtBeginning = (I == BB->begin());
+ if (!AtBeginning) --I;
+
+ // If this instruction has a FrameIndex operand, we need to
+ // use that target machine register info object to eliminate
+ // it.
+ TRI.eliminateFrameIndex(MI, SPAdj, RS);
+
+ // Reset the iterator if we were at the beginning of the BB.
+ if (AtBeginning) {
+ I = BB->begin();
+ DoIncr = false;
+ }
+
+ MI = 0;
+ break;
+ }
if (DoIncr) ++I;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Wed Mar 19 20:22:40 2008
@@ -1247,7 +1247,7 @@
ISD::SETEQ, false, DagCombineInfo);
if (!NewLHS.Val)
NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
- ISD::SETEQ);
+ ISD::SETEQ);
NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
NewLHS, Tmp1, Tmp2);
NewRHS = SDOperand();
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp Wed Mar 19 20:22:40 2008
@@ -187,9 +187,9 @@
SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
- && "SetCC type is not legal??");
+ && "SetCC type is not legal??");
return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
- N->getOperand(0), N->getOperand(1), N->getOperand(2));
+ N->getOperand(0), N->getOperand(1), N->getOperand(2));
}
SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Mar 19 20:22:40 2008
@@ -366,7 +366,7 @@
// FIXME (64-bit): Enable
NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR))
.addReg(SrcReg, false, false, isKill),
- FrameIdx));
+ FrameIdx));
return true;
} else {
// FIXME: We use R0 here, because it isn't available for RA. We need to
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Mar 19 20:22:40 2008
@@ -483,12 +483,12 @@
} else if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
BuildMI(MBB, II, TII.get(PPC::LD), Reg)
- .addImm(0)
- .addReg(PPC::X1);
+ .addImm(0)
+ .addReg(PPC::X1);
else
BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
- .addImm(0)
- .addReg(PPC::X1);
+ .addImm(0)
+ .addReg(PPC::X1);
} else {
BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
.addImm(0)
@@ -500,25 +500,25 @@
if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
BuildMI(MBB, II, TII.get(PPC::STDUX))
- .addReg(Reg, false, false, true)
- .addReg(PPC::X1)
- .addReg(MI.getOperand(1).getReg());
+ .addReg(Reg, false, false, true)
+ .addReg(PPC::X1)
+ .addReg(MI.getOperand(1).getReg());
else
BuildMI(MBB, II, TII.get(PPC::STDUX))
- .addReg(PPC::X0, false, false, true)
- .addReg(PPC::X1)
- .addReg(MI.getOperand(1).getReg());
+ .addReg(PPC::X0, false, false, true)
+ .addReg(PPC::X1)
+ .addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
- .addReg(PPC::X1)
- .addImm(maxCallFrameSize);
+ .addReg(PPC::X1)
+ .addImm(maxCallFrameSize);
else
// Implicitly kill the register.
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
- .addReg(PPC::X1)
- .addImm(maxCallFrameSize)
- .addReg(MI.getOperand(1).getReg(), false, true, true);
+ .addReg(PPC::X1)
+ .addImm(maxCallFrameSize)
+ .addReg(MI.getOperand(1).getReg(), false, true, true);
} else {
BuildMI(MBB, II, TII.get(PPC::STWUX))
.addReg(Reg, false, false, true)
@@ -527,14 +527,14 @@
if (!MI.getOperand(1).isKill())
BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
- .addReg(PPC::R1)
- .addImm(maxCallFrameSize);
+ .addReg(PPC::R1)
+ .addImm(maxCallFrameSize);
else
// Implicitly kill the register.
BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
- .addReg(PPC::R1)
- .addImm(maxCallFrameSize)
- .addReg(MI.getOperand(1).getReg(), false, true, true);
+ .addReg(PPC::R1)
+ .addImm(maxCallFrameSize)
+ .addReg(MI.getOperand(1).getReg(), false, true, true);
}
// Discard the DYNALLOC instruction.
@@ -945,7 +945,7 @@
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
- RC->getAlignment()));
+ RC->getAlignment()));
}
}
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=48577&r1=48576&r2=48577&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Mar 19 20:22:40 2008
@@ -562,9 +562,9 @@
if (isLeaf()) {
if (DefInit *DI = dynamic_cast<DefInit*>(getLeafValue())) {
if (DefInit *NDI = dynamic_cast<DefInit*>(N->getLeafValue())) {
- return ((DI->getDef() == NDI->getDef())
- && (DepVars.find(getName()) == DepVars.end()
- || getName() == N->getName()));
+ return ((DI->getDef() == NDI->getDef())
+ && (DepVars.find(getName()) == DepVars.end()
+ || getName() == N->getName()));
}
}
return getLeafValue() == N->getLeafValue();
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