[llvm-commits] [llvm] r48491 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/field-extract-use-trunc.ll
Evan Cheng
evan.cheng at apple.com
Wed Mar 19 10:58:43 PDT 2008
That's ok because legalizer will check if the type of the operand is
legal.
I think the proper fix for the dag combiner transform is to check
isTypeLegal(TruncVT).
Evan
On Mar 19, 2008, at 10:22 AM, Christopher Lamb wrote:
> This seems to be another problem, ISD::SIGN_EXTEND of MVT::i1 is
> marked as Legal, but has no ISel. I think that may be an omission in
> X86::TargetLowering, no?
>
> On Mar 19, 2008, at 1:28 AM, Bill Wendling wrote:
>
>> It's the sign-extend from MVT::i1 is the problem, it seems...
>>
>> -bw
>>
>> On Mar 19, 2008, at 12:54 AM, Christopher Lamb wrote:
>>
>>> X86 TargetLowering claims that truncate from any integer type to
>>> MVT::i1 is free. Is this correct?
>>>
>>> --
>>> Chris
>>>
>>> On Mar 18, 2008, at 3:23 PM, Bill Wendling wrote:
>>>
>>>> Hi Christopher,
>>>>
>>>> The attached testcase fails with this patch. I'm reverting it
>>>> temporarily.
>>>>
>>>> -bw
>>>>
>>>> On Tue, Mar 18, 2008 at 9:46 AM, Christopher Lamb
>>>> <christopher.lamb at gmail.com> wrote:
>>>>> Author: clamb
>>>>> Date: Tue Mar 18 11:46:39 2008
>>>>> New Revision: 48491
>>>>>
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=48491&view=rev
>>>>> Log:
>>>>> Target independent DAG transform to use truncate for field
>>>>> extraction + sign extend on targets where this is profitable.
>>>>> Passes nightly on x86-64.
>>>>>
>>>>> Added:
>>>>> llvm/trunk/test/CodeGen/X86/field-extract-use-trunc.ll
>>>>> Modified:
>>>>> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>>
>>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=48491&r1=48490&r2=48491&view=diff
>>>>>
>>>>>
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> ==================================================================
>>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>>> (original)
>>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Mar
>>>>> 18 11:46:39 2008
>>>>> @@ -2374,6 +2374,32 @@
>>>>> DAG.getValueType(EVT));
>>>>> }
>>>>>
>>>>> + // fold sra (shl X, m), result_size - n
>>>>> + // -> (sign_extend (trunc (shl X, result_size - n - m))) for
>>>>> + // result_size - n != m. If truncate is free for the target
>>>>> sext(shl) is
>>>>> + // likely to result in better code.
>>>>> + if (N0.getOpcode() == ISD::SHL) {
>>>>> + // Get the two constanst of the shifts, CN0 = m, CN = n.
>>>>> + const ConstantSDNode *N01C =
>>>>> dyn_cast<ConstantSDNode>(N0.getOperand(1));
>>>>> + if (N01C && N1C) {
>>>>> + // Determine if the truncate type's bitsize would
>>>>> correspond to
>>>>> + // an integer type for this target.
>>>>> + unsigned VTValSize = MVT::getSizeInBits(VT);
>>>>> + MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize -
>>>>> N1C->getValue());
>>>>> + unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
>>>>> +
>>>>> + // If the shift wouldn't be a noop, the truncated type
>>>>> is an actual type,
>>>>> + // and the truncate is free, then proceed with the
>>>>> transform.
>>>>> + if (ShiftAmt != 0 &&
>>>>> + !MVT::isExtendedVT(TruncVT) &&
>>>>> TLI.isTruncateFree(VT, TruncVT)) {
>>>>> + SDOperand Amt = DAG.getConstant(ShiftAmt,
>>>>> TLI.getShiftAmountTy());
>>>>> + SDOperand Shift = DAG.getNode(ISD::SRL, VT,
>>>>> N0.getOperand(0), Amt);
>>>>> + SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT,
>>>>> Shift);
>>>>> + return DAG.getNode(ISD::SIGN_EXTEND, N-
>>>>> >getValueType(0), Trunc);
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> +
>>>>> // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
>>>>> if (N1C && N0.getOpcode() == ISD::SRA) {
>>>>> if (ConstantSDNode *C1 =
>>>>> dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
>>>>>
>>>>> Added: llvm/trunk/test/CodeGen/X86/field-extract-use-trunc.ll
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/field-extract-use-trunc.ll?rev=48491&view=auto
>>>>>
>>>>>
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> ==================================================================
>>>>> --- llvm/trunk/test/CodeGen/X86/field-extract-use-trunc.ll
>>>>> (added)
>>>>> +++ llvm/trunk/test/CodeGen/X86/field-extract-use-trunc.ll Tue
>>>>> Mar 18 11:46:39 2008
>>>>> @@ -0,0 +1,39 @@
>>>>> +; RUN: llvm-as < %s | llc -march=x86 | grep sar | count 1
>>>>> +; RUN: llvm-as < %s | llc -march=x86-64 | not grep sar
>>>>> +
>>>>> +define i32 @test(i32 %f12) {
>>>>> + %tmp7.25 = lshr i32 %f12, 16
>>>>> + %tmp7.26 = trunc i32 %tmp7.25 to i8
>>>>> + %tmp78.2 = sext i8 %tmp7.26 to i32
>>>>> + ret i32 %tmp78.2
>>>>> +}
>>>>> +
>>>>> +define i32 @test2(i32 %f12) {
>>>>> + %f11 = shl i32 %f12, 8
>>>>> + %tmp7.25 = ashr i32 %f11, 24
>>>>> + ret i32 %tmp7.25
>>>>> +}
>>>>> +
>>>>> +define i32 @test3(i32 %f12) {
>>>>> + %f11 = shl i32 %f12, 13
>>>>> + %tmp7.25 = ashr i32 %f11, 24
>>>>> + ret i32 %tmp7.25
>>>>> +}
>>>>> +
>>>>> +define i64 @test4(i64 %f12) {
>>>>> + %f11 = shl i64 %f12, 32
>>>>> + %tmp7.25 = ashr i64 %f11, 32
>>>>> + ret i64 %tmp7.25
>>>>> +}
>>>>> +
>>>>> +define i16 @test5(i16 %f12) {
>>>>> + %f11 = shl i16 %f12, 2
>>>>> + %tmp7.25 = ashr i16 %f11, 8
>>>>> + ret i16 %tmp7.25
>>>>> +}
>>>>> +
>>>>> +define i16 @test6(i16 %f12) {
>>>>> + %f11 = shl i16 %f12, 8
>>>>> + %tmp7.25 = ashr i16 %f11, 8
>>>>> + ret i16 %tmp7.25
>>>>> +}
>>>>> \ No newline at end of file
>>>>>
>>>>>
>>>>> _______________________________________________
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>>>>>
>>>>> <bugpoint-reduced-simplified.bc>
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>>>
>>> --
>>> Christopher Lamb
>>>
>>>
>>>
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>>
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>
> --
> Christopher Lamb
>
>
>
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