[llvm-commits] [llvm] r48356 - /llvm/trunk/lib/Target/X86/README.txt
Evan Cheng
evan.cheng at apple.com
Mon Mar 17 11:44:12 PDT 2008
On Mar 16, 2008, at 7:24 PM, Chris Lattner wrote:
>
> On Mar 15, 2008, at 2:01 PM, Christopher Lamb wrote:
>
>> Here's a proposed solution. It seems to work OK for me. It'll be
>> even better when the undef and insert_subreg coalescing support gets
>> done.
>
> Thanks for tackling this! Could this be done as a target independent
> dag combine by selecting to "sext_in_reg(shrl)" when sext_in_reg is
> available (or before legalize)? This avoids the apparent size changes
> of the register. On PPC, for example, this would codegen to:
I am not sure about utilizing sext_in_reg, is that correct?
However, this can definitely be target independent. There is a
TLI.isTruncateFree() that you can check to ensure using truncate is
profitable.
+ if (CN->getValue() == ValueSize - 8) {
+ TruncVT = MVT::i8;
+ } else if (CN->getValue() == ValueSize - 16) {
+ TruncVT = MVT::i16;
+ } else if (CN->getValue() == ValueSize - 32) {
+ TruncVT = MVT::i32;
+ }
+
+ if (TruncVT != MVT::isVoid) {
Please just use early exit:
} else {
return SDOperand();
}
It's just a matter of style, but checking TruncVT is not MVT::isVoid
seems weird to me.
Thanks!
Evan
>
>
> _test:
> srwi r2, r3, 16
> extsb r3, r2
> blr
>
> instead of:
>
> _test2:
> slwi r2, r3, 8
> srawi r3, r2, 24
> blr
>
> On X86, this is a win because sextinreg (aka movsbl and friends) are
> 3-
> address, but sar is 2-address, giving:
>
> _test:
> shrl $16, %edi
> movsbl %dil, %eax
> ret
>
> instead of:
>
> _test2:
> shll $8, %edi
> movl %edi, %eax
> sarl $24, %eax
> ret
>
> What do you think?
>
> -Chris
>
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