[llvm-commits] [llvm] r47658 - in /llvm/trunk: lib/Target/X86/README-X86-64.txt lib/Target/X86/X86Instr64bit.td test/CodeGen/X86/x86-64-and-mask.ll

[Evan Cheng]

We still need to teach the coalescer about subreg_insert. It should be  
fairly straight forward. Just do roughly what it is doing for  
extract_subreg but making sure the resulting register is the  
definition (the larger) register instead of the source register.

Evan

On Mar 9, 2008, at 11:21 PM, Chris Lattner wrote:

>
> On Mar 9, 2008, at 11:19 PM, Christopher Lamb wrote:
>
>> My understanding is that doing the patterns this way, rather than
>> with the AsmPrinter hack, will improve JIT code quality on x86-64,  
>> no?
>
> I don't think it will improve the quality of the code generated, but
> it eliminates actual instruction definitions from the target, which
> means that there are fewer encodings to handle etc.
>
> The relative performance depends on how well the coalescer works for
> subregs vs the previous hack.
>
> -Chris
>
>
>> --
>> Christopher Lamb
>>
>> On Mar 9, 2008, at 10:37 PM, Chris Lattner wrote:
>>
>>>
>>> On Mar 9, 2008, at 10:29 PM, Christopher Lamb wrote:
>>>
>>>>
>>>> On Mar 9, 2008, at 10:17 PM, Chris Lattner wrote:
>>>>
>>>>>
>>>>> On Mar 9, 2008, at 9:28 PM, Christopher Lamb wrote:
>>>>>
>>>>>> I've prepared a change locally that allows you to write the
>>>>>> following:
>>>>>>
>>>>>> // r & (2^32-1)
>>>>>> def : Pat<(and GR64:$src, i64immFFFFFFFF),
>>>>>>          (INSERT_SUBREG x86_impl_val_zero,
>>>>>>            (MOV32rr (EXTRACT_SUBREG GR64:$src,
>>>>>> x86_subreg_32bit)),
>>>>>>            x86_subreg_32bit)>;
>>>>>
>>>>> Woot, very nifty!  In td files, we generally use lower case for
>>>>> nodes, should 'INSERT_SUBREG' -> 'insert_subreg'?
>>>>
>>>> insert_subreg, the SDNode has existed since the first subreg
>>>> support went in. This is for selecting to an INSERT_SUBREG target
>>>> instruction.
>>>>
>>> Oh right, makes sense.
>>>
>>> -Chris
>>
>>
>>
>>
>
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