[llvm-commits] [llvm] r48223 - in /llvm/trunk/lib: CodeGen/LowerSubregs.cpp CodeGen/SelectionDAG/ScheduleDAG.cpp Target/Target.td Target/X86/X86ISelDAGToDAG.cpp Target/X86/X86InstrInfo.h Target/X86/X86InstrInfo.td Target/X86/X86RegisterInfo.h Target/X86/X86RegisterInfo.td

[Evan Cheng]

>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=48223&r1=48222&r2=48223&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Mar 11 05:09:17 2008
> @@ -46,6 +46,14 @@
>     COND_INVALID
>   };
>
> +  // X86 specific implict values used for subregister inserts.
> +  // This can be used to model the fact that x86-64 by default
> +  // inserts 32-bit values into 64-bit registers implicitly  
> containing zeros.
> +  enum ImplicitVal {
> +    IMPL_VAL_UNDEF = 0,
> +    IMPL_VAL_ZERO  = 1
> +  };
> +

Rather than some magic target specific implicit value. Why not just  
allow ISD::UNDEF? That is, allow the superreg operand of INSERT_SUBREG  
as either a register, an immediate, or a ISD::UNDEF node?

Evan


>
>   // Turn condition code into conditional branch opcode.
>   unsigned GetCondBranchFromCond(CondCode CC);
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=48223&r1=48222&r2=48223&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 11 05:09:17 2008
> @@ -161,6 +161,10 @@
> // Branch targets have OtherVT type.
> def brtarget : Operand<OtherVT>;
>
> +// These should match the enum X86::ImplicitVal
> +def x86_impl_val_undef : PatLeaf<(i32 0)>;
> +def x86_impl_val_zero  : PatLeaf<(i32 1)>;
> +
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> // X86 Complex Pattern Definitions.
> //
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=48223&r1=48222&r2=48223&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Tue Mar 11 05:09:17  
> 2008
> @@ -32,6 +32,15 @@
>   };
> }
>
> +namespace X86 {
> +  /// SubregIndex - The index of various sized subregister classes.  
> Note that
> +  /// these indices must be kept in sync with the class indices in  
> the
> +  /// X86RegisterInfo.td file.
> +  enum SubregIndex {
> +    SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3
> +  };
> +}
> +
> /// DWARFFlavour - Flavour of dwarf regnumbers
> ///
> namespace DWARFFlavour {
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=48223&r1=48222&r2=48223&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Mar 11 05:09:17  
> 2008
> @@ -176,6 +176,10 @@
> // sub registers for each register.
> //
>
> +def x86_subreg_8bit    : PatLeaf<(i32 1)>;
> +def x86_subreg_16bit   : PatLeaf<(i32 2)>;
> +def x86_subreg_32bit   : PatLeaf<(i32 3)>;
> +
> def : SubRegSet<1, [AX, CX, DX, BX, SP,  BP,  SI,  DI,
>                     R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
>                    [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
>
>
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