[llvm-commits] [llvm] r48197 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/IA64/IA64ISelLowering.h test/CodeGen/CellSPU/icmp32.ll

[Scott Michel]

Author: pingbak
Date: Mon Mar 10 18:49:09 2008
New Revision: 48197

URL: http://llvm.org/viewvc/llvm-project?rev=48197&view=rev
Log:
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/IA64/IA64ISelLowering.h
    llvm/trunk/test/CodeGen/CellSPU/icmp32.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=48197&r1=48196&r2=48197&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Mar 10 18:49:09 2008
@@ -122,9 +122,6 @@
   setUseUnderscoreLongJmp(true);
     
   // Set up the SPU's register classes:
-  // NOTE: i8 register class is not registered because we cannot determine when
-  // we need to zero or sign extend for custom-lowered loads and stores.
-  // NOTE: Ignore the previous note. For now. :-)
   addRegisterClass(MVT::i8,   SPU::R8CRegisterClass);
   addRegisterClass(MVT::i16,  SPU::R16CRegisterClass);
   addRegisterClass(MVT::i32,  SPU::R32CRegisterClass);
@@ -243,22 +240,19 @@
 
   setOperationAction(ISD::CTLZ , MVT::i32,   Legal);
   
-  // SPU has a version of select
+  // SPU has a version of select that implements (a&~c)|(b|c), just like
+  // select ought to work:
   setOperationAction(ISD::SELECT, MVT::i1,   Promote);
   setOperationAction(ISD::SELECT, MVT::i8,   Legal);
   setOperationAction(ISD::SELECT, MVT::i16,  Legal);
   setOperationAction(ISD::SELECT, MVT::i32,  Legal);
   setOperationAction(ISD::SELECT, MVT::i64,  Expand);
-  setOperationAction(ISD::SELECT, MVT::f32,  Expand);
-  setOperationAction(ISD::SELECT, MVT::f64,  Expand);
 
   setOperationAction(ISD::SETCC, MVT::i1,    Promote);
   setOperationAction(ISD::SETCC, MVT::i8,    Legal);
   setOperationAction(ISD::SETCC, MVT::i16,   Legal);
   setOperationAction(ISD::SETCC, MVT::i32,   Legal);
   setOperationAction(ISD::SETCC, MVT::i64,   Expand);
-  setOperationAction(ISD::SETCC, MVT::f32,   Expand);
-  setOperationAction(ISD::SETCC, MVT::f64,   Expand);
 
   // Zero extension and sign extension for i64 have to be
   // custom legalized
@@ -449,7 +443,11 @@
 
 MVT::ValueType
 SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
-  return Op.getValueType();
+  MVT::ValueType VT = Op.getValueType();
+  if (MVT::isInteger(VT))
+    return VT;
+  else
+    return MVT::i32;
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.h?rev=48197&r1=48196&r2=48197&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelLowering.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.h Mon Mar 10 18:49:09 2008
@@ -47,7 +47,9 @@
     unsigned VirtGPR; // this is public so it can be accessed in the selector
                       // for ISD::RET. add an accessor instead? FIXME
     const char *getTargetNodeName(unsigned Opcode) const;
-    MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
+    /// getSetCCResultType: return ISD::SETCC's result type.
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
       
     /// LowerArguments - This hook must be implemented to indicate how we should
     /// lower the arguments for the specified function, into the specified DAG.

Modified: llvm/trunk/test/CodeGen/CellSPU/icmp32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/icmp32.ll?rev=48197&r1=48196&r2=48197&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/icmp32.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/icmp32.ll Mon Mar 10 18:49:09 2008
@@ -1,4 +1,14 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep ila                                %t1.s | count 6
+; RUN: grep ceq                                %t1.s | count 28
+; RUN: grep ceqi                               %t1.s | count 11
+; RUN: grep clgt                               %t1.s | count 16
+; RUN: grep clgti                              %t1.s | count 5
+; RUN: grep cgt                                %t1.s | count 16
+; RUN: grep cgti                               %t1.s | count 6
+; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 20
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"