[llvm-commits] [llvm] r48140 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Evan Cheng evan.cheng at apple.com
Mon Mar 10 12:43:30 PDT 2008


On Mar 10, 2008, at 11:44 AM, Chris Lattner wrote:

> On Mar 10, 2008, at 12:59 AM, Evan Cheng wrote:
>> Author: evancheng
>> Date: Mon Mar 10 02:59:01 2008
>> New Revision: 48140
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=48140&view=rev
>> Log:
>> Doh
>
> I'm not sure if this is the right thing to do.  How about only doing
> this xform (x-x => 0) if before legalize or if the element is a
> scalar?

Yep, that's the right thing to do. I had a brain cramp last night.

>  Alternatively, dag combiner should query the target to see if
> the result is valid, it shouldn't just disable it for build vectors.

The problem is BUILD_VECTOR v8i16 is legal. But since x86 normalized  
BUILD_VECTOR of all zero to v4i32 (to allow CSE) it doesn't have the  
isel rules to select the other variants. I don't want to add the rules  
for other types if it can be avoided.

Evan
>
>
> -Chris
>
>>
>>
>> Modified:
>>   llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=48140&r1=48139&r2=48140&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 10
>> 02:59:01 2008
>> @@ -1102,12 +1102,13 @@
>>  }
>>
>>  // fold (sub x, x) -> 0
>> -  if (N0 == N1)
>> +  if (N0 == N1) {
>>    if (ISD::isBuildVectorAllZeros(N0.Val))
>>      // Zero vectors might be normalized to a particular vector
>> type to ensure
>>      // they are CSE'd. Return it as it is.
>>      return N0;
>>    return DAG.getConstant(0, N->getValueType(0));
>> +  }
>>  // fold (sub c1, c2) -> c1-c2
>>  if (N0C && N1C)
>>    return DAG.getNode(ISD::SUB, VT, N0, N1);
>>
>>
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