[llvm-commits] [llvm] r47658 - in /llvm/trunk: lib/Target/X86/README-X86-64.txt lib/Target/X86/X86Instr64bit.td test/CodeGen/X86/x86-64-and-mask.ll

[Christopher Lamb]

On Mar 9, 2008, at 10:17 PM, Chris Lattner wrote:

>
> On Mar 9, 2008, at 9:28 PM, Christopher Lamb wrote:
>
>> I've prepared a change locally that allows you to write the  
>> following:
>>
>> // r & (2^32-1)
>> def : Pat<(and GR64:$src, i64immFFFFFFFF),
>>           (INSERT_SUBREG x86_impl_val_zero,
>>             (MOV32rr (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)),
>>             x86_subreg_32bit)>;
>
> Woot, very nifty!  In td files, we generally use lower case for  
> nodes, should 'INSERT_SUBREG' -> 'insert_subreg'?

insert_subreg, the SDNode has existed since the first subreg support  
went in. This is for selecting to an INSERT_SUBREG target instruction.

--
Christopher Lamb

>> On Mar 8, 2008, at 2:18 PM, Chris Lattner wrote:
>>
>>> One very simple and nice thing we could do is replace the  
>>> duplicated instruction with a Pat pattern.  This would mean that  
>>> there is only one instruction and the magic just happens in the  
>>> isel.  This would give us something like this:
>>>
>>> def : Pat<(and GR64:$src, i64immFFFFFFFF),
>>>           (x86_64_bit_part_of_32_bit
>>>              (MOV32rr (subreg GR64:$src,  
>>> x86_32bit_part_of_64bit)))>;
>>>
>>> This puts more pressure on the coalescer to coalesce away the  
>>> copies, but seems like an overall better solution.  Is this the  
>>> sort of thing you mean?
>>
>> --
>> Christopher Lamb
>>
>>
>>
>





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