[llvm-commits] [llvm] r48118 - /llvm/trunk/lib/Target/IA64/IA64RegisterInfo.td

[Chris Lattner]

Author: lattner
Date: Sun Mar  9 15:12:44 2008
New Revision: 48118

URL: http://llvm.org/viewvc/llvm-project?rev=48118&view=rev
Log:
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll


Modified:
    llvm/trunk/lib/Target/IA64/IA64RegisterInfo.td

Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.td?rev=48118&r1=48117&r2=48118&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.td Sun Mar  9 15:12:44 2008
@@ -418,8 +418,9 @@
         r96, r97, r98, r99, r100, r101, r102, r103,
         r104, r105, r106, r107, r108, r109, r110, r111,
         r112, r113, r114, r115, r116, r117, r118, r119,
+        // last 17 are special (look down)
         r120, r121, r122, r123, r124, r125, r126, r127,
-        r0, r1, r2, r5, r12, r13, r22, rp]> // last 16 are special (look down)
+        r0, r1, r2, r5, r12, r13, r22, rp, AR_PFS]>
   {
     let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
@@ -434,8 +435,9 @@
 
       GRClass::iterator
       GRClass::allocation_order_end(const MachineFunction &MF) const {
-        int numReservedRegs=8;// the 8 special registers r0,r1,r2,r5,r12,r13 etc
-
+        // the 9 special registers r0,r1,r2,r5,r12,r13 etc
+        int numReservedRegs=9;
+        
         // we also can't allocate registers for use as locals if they're already
         // required as 'out' registers
         numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;