[llvm-commits] [llvm] r47658 - in /llvm/trunk: lib/Target/X86/README-X86-64.txt lib/Target/X86/X86Instr64bit.td test/CodeGen/X86/x86-64-and-mask.ll

[Christopher Lamb]

This is very close to what I propose, though the  
'x86_32bit_part_of_64bit' part is only necessary on the insert. See  
below:


(insert_subreg
	(MOV32rr (extract_subreg GR64:$src, x86_64_32bit_subreg_idx)),  
x86_64_implict_zext, x86_64_32bit_subreg_idx)


This means there are two insert_subreg forms, the normal input form

insert_subreg superregOutOutput, subregInOperand,  
superregInOperandToInsertInto, immediateSubregIndex

and as second form for these target dependent inserts

insert_subreg superregOutOutput, subregInOperand,  
immediateTargetKindFlag, immediateSubregIndex

The trick about the second form is even though the semantics are  
target dependent, the coalescer need not know about these target  
dependent semantics to coalesce the it.

--
Christopher Lamb

On Mar 8, 2008, at 2:18 PM, Chris Lattner wrote:

> Right now we have:
>
> def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
>                 "mov{l}\t{$src, $dst|$dst, $src}", []>;
> and:
>
> def PsAND64rrFFFFFFFF
>   : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
>       "mov{l}\t{${src:subreg32}, ${dst:subreg32}|${dst:subreg32}, $ 
> {src:subreg32}}",
>       [(set GR64:$dst, (and GR64:$src, i64immFFFFFFFF))]>;
>
> One very simple and nice thing we could do is replace the  
> duplicated instruction with a Pat pattern.  This would mean that  
> there is only one instruction and the magic just happens in the  
> isel.  This would give us something like this:
>
> def : Pat<(and GR64:$src, i64immFFFFFFFF),
>           (x86_64_bit_part_of_32_bit
>              (MOV32rr (subreg GR64:$src, x86_32bit_part_of_64bit)))>;
>
> This puts more pressure on the coalescer to coalesce away the  
> copies, but seems like an overall better solution.  Is this the  
> sort of thing you mean?
>
> -Chris