[llvm-commits] [llvm] r48026 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

[Chris Lattner]

Author: lattner
Date: Fri Mar  7 14:13:51 2008
New Revision: 48026

URL: http://llvm.org/viewvc/llvm-project?rev=48026&view=rev
Log:
Replace SDT_PPCShiftOp in favor of SDTIntBinOps.  This allows it to work
with 32 or 64-bit operands/results.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=48026&r1=48025&r2=48026&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Fri Mar  7 14:13:51 2008
@@ -20,9 +20,6 @@
 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
   SDTCisVT<0, f64>, SDTCisPtrTy<1>
 ]>;
-def SDT_PPCShiftOp : SDTypeProfile<1, 2, [   // PPCshl, PPCsra, PPCsrl
-  SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
-]>;
 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
 def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
                                          SDTCisVT<1, i32> ]>;
@@ -84,9 +81,9 @@
 
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
 // amounts.  These nodes are generated by the multi-precision shift code.
-def PPCsrl        : SDNode<"PPCISD::SRL"       , SDT_PPCShiftOp>;
-def PPCsra        : SDNode<"PPCISD::SRA"       , SDT_PPCShiftOp>;
-def PPCshl        : SDNode<"PPCISD::SHL"       , SDT_PPCShiftOp>;
+def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntBinOp>;
+def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntBinOp>;
+def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntBinOp>;
 
 def PPCextsw_32   : SDNode<"PPCISD::EXTSW_32"  , SDTIntUnaryOp>;
 def PPCstd_32     : SDNode<"PPCISD::STD_32"    , SDTStore,