[llvm-commits] [llvm] r47992 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll

Evan Cheng evan.cheng at apple.com
Thu Mar 6 00:20:52 PST 2008


Author: evancheng
Date: Thu Mar  6 02:20:51 2008
New Revision: 47992

URL: http://llvm.org/viewvc/llvm-project?rev=47992&view=rev
Log:
Constant fold SIGN_EXTEND_INREG with ashr not lshr.

Added:
    llvm/trunk/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47992&r1=47991&r2=47992&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Mar  6 02:20:51 2008
@@ -2029,7 +2029,7 @@
       APInt Val = N1C->getAPIntValue();
       unsigned FromBits = MVT::getSizeInBits(cast<VTSDNode>(N2)->getVT());
       Val <<= Val.getBitWidth()-FromBits;
-      Val = Val.lshr(Val.getBitWidth()-FromBits);
+      Val = Val.ashr(Val.getBitWidth()-FromBits);
       return getConstant(Val, VT);
     }
     break;

Added: llvm/trunk/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll?rev=47992&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll Thu Mar  6 02:20:51 2008
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | not grep 255
+
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+	br label %bb1
+bb1:		; preds = %entry
+	%tmp3.i.i = load i8* null, align 1		; <i8> [#uses=1]
+	%tmp4.i.i = icmp slt i8 %tmp3.i.i, 0		; <i1> [#uses=1]
+	br i1 %tmp4.i.i, label %bb2, label %bb3
+bb2:		; preds = %bb1
+	ret i32 1
+bb3:		; preds = %bb1
+	ret i32 0
+}





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