[llvm-commits] [llvm] r47915 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrInfo.cpp PPCRegisterInfo.cpp
Bill Wendling
isanbard at gmail.com
Tue Mar 4 15:13:51 PST 2008
Author: void
Date: Tue Mar 4 17:13:51 2008
New Revision: 47915
URL: http://llvm.org/viewvc/llvm-project?rev=47915&view=rev
Log:
Use a command-line option to turn register scavenging on/off for PPC.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=47915&r1=47914&r2=47915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Mar 4 17:13:51 2008
@@ -19,8 +19,11 @@
#include "PPCTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Support/CommandLine.h"
using namespace llvm;
+extern cl::opt<bool> EnablePPCRS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
+
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
RI(*TM.getSubtargetImpl(), *this) {}
@@ -320,8 +323,7 @@
static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs,
- bool isPPC64/*FIXME (64-bit): Remove.*/) {
+ SmallVectorImpl<MachineInstr*> &NewMIs) {
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
@@ -353,7 +355,7 @@
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) {
- if (!isPPC64) { // FIXME (64-bit): Enable
+ if (EnablePPCRS) { // FIXME (64-bit): Enable
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR))
.addReg(SrcReg, false, false, isKill),
FrameIdx));
@@ -402,8 +404,7 @@
const TargetRegisterClass *RC) const {
SmallVector<MachineInstr*, 4> NewMIs;
- if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs,
- TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) {
+ if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
FuncInfo->setSpillsCR();
}
@@ -418,8 +419,8 @@
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const{
if (Addr[0].isFrameIndex()) {
- if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs,
- TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) {
+ if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(),
+ RC, NewMIs)) {
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
FuncInfo->setSpillsCR();
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=47915&r1=47914&r2=47915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 4 17:13:51 2008
@@ -42,10 +42,16 @@
#include <cstdlib>
using namespace llvm;
+// FIXME (64-bit): Eventually enable by default.
+cl::opt<bool> EnablePPCRS("enable-ppc-regscavenger",
+ cl::init(false),
+ cl::desc("enable PPC register scavenger"),
+ cl::Hidden);
+
// FIXME (64-bit): Should be inlined.
bool
PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
- return !Subtarget.isPPC64();
+ return EnablePPCRS;
}
/// getRegisterNumbering - Given the enum value for some register, e.g.
@@ -310,7 +316,8 @@
Reserved.set(PPC::R13);
Reserved.set(PPC::R31);
- Reserved.set(PPC::R0); // FIXME (64-bit): Remove
+ if (!EnablePPCRS)
+ Reserved.set(PPC::R0); // FIXME (64-bit): Remove
Reserved.set(PPC::X0);
Reserved.set(PPC::X1);
@@ -414,7 +421,7 @@
// FIXME (64-bit): Use "findScratchRegister"
unsigned Reg;
- if (!LP64)
+ if (EnablePPCRS)
Reg = findScratchRegister(II, RS, RC, SPAdj);
else
Reg = PPC::R0;
@@ -424,10 +431,15 @@
.addReg(PPC::R31)
.addImm(FrameSize);
} else if (LP64) {
- Reg = PPC::X0; // FIXME (64-bit): Remove.
- BuildMI(MBB, II, TII.get(PPC::LD), Reg)
- .addImm(0)
- .addReg(PPC::X1);
+ if (!EnablePPCRS)
+ if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
+ BuildMI(MBB, II, TII.get(PPC::LD), Reg)
+ .addImm(0)
+ .addReg(PPC::X1);
+ else
+ BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
+ .addImm(0)
+ .addReg(PPC::X1);
} else {
BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
.addImm(0)
@@ -437,17 +449,16 @@
// Grow the stack and update the stack pointer link, then determine the
// address of new allocated space.
if (LP64) {
-#if 0 // FIXME (64-bit): Enable
- BuildMI(MBB, II, TII.get(PPC::STDUX))
- .addReg(Reg, false, false, true)
- .addReg(PPC::X1)
- .addReg(MI.getOperand(1).getReg());
-#else
- BuildMI(MBB, II, TII.get(PPC::STDUX))
- .addReg(PPC::X0, false, false, true)
- .addReg(PPC::X1)
- .addReg(MI.getOperand(1).getReg());
-#endif
+ if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
+ BuildMI(MBB, II, TII.get(PPC::STDUX))
+ .addReg(Reg, false, false, true)
+ .addReg(PPC::X1)
+ .addReg(MI.getOperand(1).getReg());
+ else
+ BuildMI(MBB, II, TII.get(PPC::STDUX))
+ .addReg(PPC::X0, false, false, true)
+ .addReg(PPC::X1)
+ .addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
@@ -573,11 +584,11 @@
}
// Special case for pseudo-op SPILL_CR.
- if (!Subtarget.isPPC64()) // FIXME (64-bit): Remove.
- if (OpC == PPC::SPILL_CR) {
- lowerCRSpilling(II, FrameIndex, SPAdj, RS);
- return;
- }
+ if (EnablePPCRS) // FIXME (64-bit): Enable by default
+ if (OpC == PPC::SPILL_CR) {
+ lowerCRSpilling(II, FrameIndex, SPAdj, RS);
+ return;
+ }
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
@@ -627,7 +638,7 @@
// FIXME (64-bit): Use "findScratchRegister".
unsigned SReg;
- if (!Subtarget.isPPC64())
+ if (EnablePPCRS)
SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
else
SReg = PPC::R0;
@@ -879,14 +890,14 @@
// FIXME: doesn't detect whether or not we need to spill vXX, which requires
// r0 for now.
- if (!IsPPC64) // FIXME (64-bit): Enable.
- if (needsFP(MF) || spillsCR(MF)) {
- const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
- const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
- const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
- RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
- RC->getAlignment()));
- }
+ if (EnablePPCRS) // FIXME (64-bit): Enable.
+ if (needsFP(MF) || spillsCR(MF)) {
+ const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
+ const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
+ const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
+ RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
+ RC->getAlignment()));
+ }
}
void
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