[llvm-commits] [llvm] r47868 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Dan Gohman]

Author: djg
Date: Mon Mar  3 17:35:36 2008
New Revision: 47868

URL: http://llvm.org/viewvc/llvm-project?rev=47868&view=rev
Log:
More APInt-ification.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47868&r1=47867&r2=47868&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Mar  3 17:35:36 2008
@@ -1518,17 +1518,13 @@
     return VTBits-Tmp;
     
   case ISD::Constant: {
-    uint64_t Val = cast<ConstantSDNode>(Op)->getValue();
-    // If negative, invert the bits, then look at it.
-    if (Val & MVT::getIntVTSignBit(VT))
-      Val = ~Val;
-    
-    // Shift the bits so they are the leading bits in the int64_t.
-    Val <<= 64-VTBits;
-    
-    // Return # leading zeros.  We use 'min' here in case Val was zero before
-    // shifting.  We don't want to return '64' as for an i32 "0".
-    return std::min(VTBits, CountLeadingZeros_64(Val));
+    const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
+    // If negative, return # leading ones.
+    if (Val.isNegative())
+      return Val.countLeadingOnes();
+    
+    // Return # leading zeros.
+    return Val.countLeadingZeros();
   }
     
   case ISD::SIGN_EXTEND: