[llvm-commits] [llvm] r47554 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Evan Cheng
evan.cheng at apple.com
Mon Feb 25 13:15:28 PST 2008
On Feb 25, 2008, at 11:49 AM, Dale Johannesen wrote:
>
> On Feb 25, 2008, at 11:44 AM, Evan Cheng wrote:
>
>>
>> On Feb 25, 2008, at 11:20 AM, Dale Johannesen wrote:
>>
>>> const X86Subtarget *Subtarget) {
>>>
>>> + // Must be a store of a load. We currently handle two cases:
>>> the load
>>> + // is a direct child, and it's under an intervening
>>> TokenFactor. It is
>>> + // possible to dig deeper under nested TokenFactors.
>>> + if (ChainVal == St->getValue().Val)
>>> + Ld = cast<LoadSDNode>(St->getChain());
>>
>> I'm not sure how safe this is. It can be storing a value produced by
>> any chain producing node. Can it be a CopyFromReg?
>>
>> Evan
>
> It is checked above that St->getValue() is a load. Is that not
> enough?
Ok. Can you put ST->getValue() in an appropriately named variable to
help me understand the code? Thanks.
Evan
>
>
>>> + else if (St->getValue().hasOneUse() &&
>>> + ChainVal->getOpcode() == ISD::TokenFactor) {
>>> + for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; +
>>> +i) {
>>> + if (ChainVal->getOperand(i).Val == St->getValue().Val) {
>>> + if (TokenFactorIndex != -1)
>>> + return SDOperand();
>>> + TokenFactorIndex = i;
>>> + Ld = cast<LoadSDNode>(St->getValue());
>>> + } else
>>> + Ops.push_back(ChainVal->getOperand(i));
>>> + }
>>> + }
>>> + if (Ld) {
>>> + // If we are a 64-bit capable x86, lower to a single movq
>>> load/store pair.
>>> + if (Subtarget->is64Bit()) {
>>> + SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
>>> + Ld->getBasePtr(), Ld-
>>>> getSrcValue(),
>>> + Ld->getSrcValueOffset(), Ld-
>>>> isVolatile(),
>>> + Ld->getAlignment());
>>> + SDOperand NewChain = NewLd.getValue(1);
>>> + if (TokenFactorIndex != -1) {
>>> + Ops.push_back(NewLd);
>>> + NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
>>> &Ops[0],
>>> + Ops.size());
>>> + }
>>> + return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
>>> + St->getSrcValue(), St-
>>>> getSrcValueOffset(),
>>> + St->isVolatile(), St->getAlignment());
>>> + }
>>> +
>>> + // Otherwise, lower to two 32-bit copies.
>>> + SDOperand LoAddr = Ld->getBasePtr();
>>> + SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
>>> + DAG.getConstant(MVT::i32, 4));
>>> +
>>> + SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(),
>>> LoAddr,
>>> + Ld->getSrcValue(), Ld-
>>>> getSrcValueOffset(),
>>> + Ld->isVolatile(), Ld-
>>>> getAlignment());
>>> + SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(),
>>> HiAddr,
>>> + Ld->getSrcValue(), Ld-
>>>> getSrcValueOffset()+4,
>>> + Ld->isVolatile(),
>>> + MinAlign(Ld->getAlignment(),
>>> 4));
>>> +
>>> + SDOperand NewChain = LoLd.getValue(1);
>>> + if (TokenFactorIndex != -1) {
>>> + Ops.push_back(LoLd);
>>> + Ops.push_back(HiLd);
>>> + NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
>>> &Ops[0],
>>> + Ops.size());
>>> + }
>>> +
>>> + LoAddr = St->getBasePtr();
>>> + HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
>>> + DAG.getConstant(MVT::i32, 4));
>>> +
>>> + SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
>>> St->getSrcValue(), St->getSrcValueOffset(),
>>> St->isVolatile(), St->getAlignment());
>>> + SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
>>> + St->getSrcValue(), St-
>>>> getSrcValueOffset()+4,
>>> + St->isVolatile(),
>>> + MinAlign(St->getAlignment(),
>>> 4));
>>> + return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
>>> }
>>> -
>>> - // Otherwise, lower to two 32-bit copies.
>>> - SDOperand LoAddr = Ld->getBasePtr();
>>> - SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
>>> - DAG.getConstant(MVT::i32, 4));
>>> -
>>> - SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
>>> - Ld->getSrcValue(), Ld-
>>>> getSrcValueOffset(),
>>> - Ld->isVolatile(), Ld-
>>>> getAlignment());
>>> - SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
>>> - Ld->getSrcValue(), Ld-
>>>> getSrcValueOffset()+4,
>>> - Ld->isVolatile(),
>>> - MinAlign(Ld->getAlignment(), 4));
>>> -
>>> - LoAddr = St->getBasePtr();
>>> - HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
>>> - DAG.getConstant(MVT::i32, 4));
>>> -
>>> - SDOperand LoSt = DAG.getStore(LoLd.getValue(1), LoLd, LoAddr,
>>> - St->getSrcValue(), St->getSrcValueOffset(),
>>> - St->isVolatile(), St->getAlignment());
>>> - SDOperand HiSt = DAG.getStore(HiLd.getValue(1), HiLd, HiAddr,
>>> - St->getSrcValue(), St-
>>>> getSrcValueOffset()+4,
>>> - St->isVolatile(),
>>> - MinAlign(St->getAlignment(), 4));
>>> - return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
>>> }
>>> return SDOperand();
>>> }
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list