[llvm-commits] [llvm] r47383 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeTypesExpand.cpp

[Dan Gohman]

Author: djg
Date: Wed Feb 20 10:57:27 2008
New Revision: 47383

URL: http://llvm.org/viewvc/llvm-project?rev=47383&view=rev
Log:
Convert Legalize to use the APInt form of ComputeMaskedBits.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47383&r1=47382&r2=47383&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 20 10:57:27 2008
@@ -5027,6 +5027,7 @@
   MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
   SDOperand ShAmt = LegalizeOp(Amt);
   MVT::ValueType ShTy = ShAmt.getValueType();
+  unsigned ShBits = MVT::getSizeInBits(ShTy);
   unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
   unsigned NVTBits = MVT::getSizeInBits(NVT);
 
@@ -5096,15 +5097,16 @@
   
   // Okay, the shift amount isn't constant.  However, if we can tell that it is
   // >= 32 or < 32, we can still simplify it, without knowing the actual value.
-  uint64_t Mask = NVTBits, KnownZero, KnownOne;
+  APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
+  APInt KnownZero, KnownOne;
   DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
   
   // If we know that the high bit of the shift amount is one, then we can do
   // this as a couple of simple shifts.
-  if (KnownOne & Mask) {
+  if (KnownOne.intersects(Mask)) {
     // Mask out the high bit, which we know is set.
     Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
-                      DAG.getConstant(NVTBits-1, Amt.getValueType()));
+                      DAG.getConstant(~Mask, Amt.getValueType()));
     
     // Expand the incoming operand to be shifted, so that we have its parts
     SDOperand InL, InH;
@@ -5128,7 +5130,7 @@
   
   // If we know that the high bit of the shift amount is zero, then we can do
   // this as a couple of simple shifts.
-  if (KnownZero & Mask) {
+  if (KnownZero.intersects(Mask)) {
     // Compute 32-amt.
     SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
                                  DAG.getConstant(NVTBits, Amt.getValueType()),

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=47383&r1=47382&r2=47383&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Wed Feb 20 10:57:27 2008
@@ -748,12 +748,16 @@
 /// shift amount.
 bool DAGTypeLegalizer::
 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
+  SDOperand Amt = N->getOperand(1);
   MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+  MVT::ValueType ShTy = Amt.getValueType();
+  MVT::ValueType ShBits = MVT::getSizeInBits(ShTy);
   unsigned NVTBits = MVT::getSizeInBits(NVT);
-  assert(!(NVTBits & (NVTBits - 1)) &&
+  assert(isPowerOf2_32(NVTBits) &&
          "Expanded integer type size not a power of two!");
 
-  uint64_t HighBitMask = NVTBits, KnownZero, KnownOne;
+  APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
+  APInt KnownZero, KnownOne;
   DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
   
   // If we don't know anything about the high bit, exit.
@@ -763,14 +767,13 @@
   // Get the incoming operand to be shifted.
   SDOperand InL, InH;
   GetExpandedOp(N->getOperand(0), InL, InH);
-  SDOperand Amt = N->getOperand(1);
 
   // If we know that the high bit of the shift amount is one, then we can do
   // this as a couple of simple shifts.
-  if (KnownOne & HighBitMask) {
+  if (KnownOne.intersects(HighBitMask)) {
     // Mask out the high bit, which we know is set.
-    Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
-                      DAG.getConstant(NVTBits-1, Amt.getValueType()));
+    Amt = DAG.getNode(ISD::AND, ShTy, Amt,
+                      DAG.getConstant(~HighBitMask, ShTy));
     
     switch (N->getOpcode()) {
     default: assert(0 && "Unknown shift");
@@ -784,7 +787,7 @@
       return true;
     case ISD::SRA:
       Hi = DAG.getNode(ISD::SRA, NVT, InH,       // Sign extend high part.
-                       DAG.getConstant(NVTBits-1, Amt.getValueType()));
+                       DAG.getConstant(NVTBits-1, ShTy));
       Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
       return true;
     }
@@ -792,11 +795,11 @@
   
   // If we know that the high bit of the shift amount is zero, then we can do
   // this as a couple of simple shifts.
-  assert((KnownZero & HighBitMask) && "Bad mask computation above");
+  assert(KnownZero.intersects(HighBitMask) && "Bad mask computation above");
 
   // Compute 32-amt.
-  SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
-                               DAG.getConstant(NVTBits, Amt.getValueType()),
+  SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
+                               DAG.getConstant(NVTBits, ShTy),
                                Amt);
   unsigned Op1, Op2;
   switch (N->getOpcode()) {