[llvm-commits] [llvm] r47369 - in /llvm/trunk/lib/Target: ARM/ARMCodeEmitter.cpp ARM/ARMISelLowering.cpp ARM/ARMRegisterInfo.cpp Alpha/AlphaRegisterInfo.cpp CBackend/CBackend.cpp IA64/IA64RegisterInfo.h MSIL/MSILWriter.cpp PowerPC/PPCISelDAGToDAG.cpp PowerPC/PPCTargetMachine.cpp X86/X86ISelLowering.cpp X86/X86IntelAsmPrinter.cpp X86/X86Subtarget.cpp X86/X86TargetMachine.cpp
Anton Korobeynikov
asl at math.spbu.ru
Wed Feb 20 03:22:42 PST 2008
Author: asl
Date: Wed Feb 20 05:22:39 2008
New Revision: 47369
URL: http://llvm.org/viewvc/llvm-project?rev=47369&view=rev
Log:
Remove bunch of gcc 4.3-related warnings from Target
Modified:
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
llvm/trunk/lib/Target/CBackend/CBackend.cpp
llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h
llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Feb 20 05:22:39 2008
@@ -475,8 +475,8 @@
}
}
// set the field related to shift operations (except rrx).
- if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
- if(IsShiftByRegister) {
+ if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
+ if (IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
@@ -487,6 +487,7 @@
op = ARM_AM::getSORegOffset(MO2.getImm());
Value |= op << 7;
}
+ }
break;
}
default: assert(false && "Unknown operand type!");
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 20 05:22:39 2008
@@ -1551,7 +1551,7 @@
if ((V & (Scale - 1)) != 0)
return false;
V /= Scale;
- return V == V & ((1LL << 5) - 1);
+ return V == (V & ((1LL << 5) - 1));
}
if (V < 0)
@@ -1562,10 +1562,10 @@
case MVT::i8:
case MVT::i32:
// +- imm12
- return V == V & ((1LL << 12) - 1);
+ return V == (V & ((1LL << 12) - 1));
case MVT::i16:
// +- imm8
- return V == V & ((1LL << 8) - 1);
+ return V == (V & ((1LL << 8) - 1));
case MVT::f32:
case MVT::f64:
if (!Subtarget->hasVFP2())
@@ -1573,7 +1573,7 @@
if ((V & 3) != 0)
return false;
V >>= 2;
- return V == V & ((1LL << 8) - 1);
+ return V == (V & ((1LL << 8) - 1));
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Wed Feb 20 05:22:39 2008
@@ -1328,7 +1328,7 @@
if (AFI->getGPRCalleeSavedArea2Size() ||
AFI->getDPRCalleeSavedAreaSize() ||
AFI->getDPRCalleeSavedAreaOffset()||
- hasFP(MF))
+ hasFP(MF)) {
if (NumBytes)
BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
.addImm(NumBytes)
@@ -1336,6 +1336,7 @@
else
BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
+ }
} else if (NumBytes) {
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
}
Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed Feb 20 05:22:39 2008
@@ -272,8 +272,8 @@
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert(MBBI->getOpcode() == Alpha::RETDAG ||
- MBBI->getOpcode() == Alpha::RETDAGp
+ assert((MBBI->getOpcode() == Alpha::RETDAG ||
+ MBBI->getOpcode() == Alpha::RETDAGp)
&& "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);
Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Feb 20 05:22:39 2008
@@ -2912,7 +2912,7 @@
HasImplicitAddress = false; // HIA is only true if we haven't addressed yet
}
- assert(!HasImplicitAddress || (CI && CI->isNullValue()) &&
+ assert((!HasImplicitAddress || (CI && CI->isNullValue())) &&
"Can only have implicit address with direct accessing");
if (HasImplicitAddress) {
Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h Wed Feb 20 05:22:39 2008
@@ -17,8 +17,6 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "IA64GenRegisterInfo.h.inc"
-namespace llvm { class llvm::Type; }
-
namespace llvm {
class TargetInstrInfo;
Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Wed Feb 20 05:22:39 2008
@@ -202,7 +202,7 @@
}
bool RetVoid = (F->getReturnType()->getTypeID() == Type::VoidTyID);
- if (BadSig || !F->getReturnType()->isInteger() && !RetVoid) {
+ if (BadSig || (!F->getReturnType()->isInteger() && !RetVoid)) {
Out << "\tldc.i4.0\n";
} else {
Out << "\tcall\t" << getTypeName(F->getReturnType()) <<
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Feb 20 05:22:39 2008
@@ -935,7 +935,7 @@
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
if (LD->getValueType(0) != MVT::i64) {
// Handle PPC32 integer and normal FP loads.
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
default: assert(0 && "Invalid PPC load type!");
case MVT::f64: Opcode = PPC::LFDU; break;
@@ -947,7 +947,7 @@
}
} else {
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
default: assert(0 && "Invalid PPC load type!");
case MVT::i64: Opcode = PPC::LDU; break;
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Feb 20 05:22:39 2008
@@ -92,11 +92,12 @@
FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
- if (getRelocationModel() == Reloc::Default)
+ if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isDarwin())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
+ }
}
/// Override this for PowerPC. Tail merging happily breaks up instruction issue
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 20 05:22:39 2008
@@ -1029,12 +1029,13 @@
CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
- if (Subtarget->is64Bit())
+ if (Subtarget->is64Bit()) {
if (CC == CallingConv::Fast && PerformTailCallOpt)
return CC_X86_64_TailCall;
else
return CC_X86_64_C;
-
+ }
+
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast && PerformTailCallOpt)
@@ -3358,11 +3359,12 @@
default: assert(false && "Unexpected!");
}
- if (NewWidth == 2)
+ if (NewWidth == 2) {
if (MVT::isInteger(VT))
NewVT = MVT::v2i64;
else
NewVT = MVT::v2f64;
+ }
unsigned Scale = NumElems / NewWidth;
SmallVector<SDOperand, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i += Scale) {
Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp Wed Feb 20 05:22:39 2008
@@ -221,13 +221,14 @@
} else {
int DispVal = DispSpec.getImm();
if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
- if (NeedPlus)
+ if (NeedPlus) {
if (DispVal > 0)
O << " + ";
else {
O << " - ";
DispVal = -DispVal;
}
+ }
O << DispVal;
}
}
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Feb 20 05:22:39 2008
@@ -36,7 +36,7 @@
bool isDirectCall) const
{
// FIXME: PIC
- if (TM.getRelocationModel() != Reloc::Static)
+ if (TM.getRelocationModel() != Reloc::Static) {
if (isTargetDarwin()) {
return (!isDirectCall &&
(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
@@ -48,6 +48,7 @@
} else if (isTargetCygMing() || isTargetWindows()) {
return (GV->hasDLLImportLinkage());
}
+ }
return false;
}
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=47369&r1=47368&r2=47369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Feb 20 05:22:39 2008
@@ -119,11 +119,12 @@
Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
DefRelocModel = getRelocationModel();
- if (getRelocationModel() == Reloc::Default)
+ if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isTargetDarwin() || Subtarget.isTargetCygMing())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
+ }
if (Subtarget.is64Bit()) {
// No DynamicNoPIC support under X86-64.
if (getRelocationModel() == Reloc::DynamicNoPIC)
@@ -135,16 +136,17 @@
if (Subtarget.isTargetCygMing())
Subtarget.setPICStyle(PICStyle::WinPIC);
- else if (Subtarget.isTargetDarwin())
+ else if (Subtarget.isTargetDarwin()) {
if (Subtarget.is64Bit())
Subtarget.setPICStyle(PICStyle::RIPRel);
else
Subtarget.setPICStyle(PICStyle::Stub);
- else if (Subtarget.isTargetELF())
+ } else if (Subtarget.isTargetELF()) {
if (Subtarget.is64Bit())
Subtarget.setPICStyle(PICStyle::RIPRel);
else
Subtarget.setPICStyle(PICStyle::GOT);
+ }
}
//===----------------------------------------------------------------------===//
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