[llvm-commits] [llvm] r47282 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Dan Gohman]

Author: djg
Date: Mon Feb 18 13:34:53 2008
New Revision: 47282

URL: http://llvm.org/viewvc/llvm-project?rev=47282&view=rev
Log:
Chris pointed out that it's not necessary to set i64 MUL to Expand
on x86-32 since i64 itself is not a Legal type. And, update some
comments.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47282&r1=47281&r2=47282&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Feb 18 13:34:53 2008
@@ -169,13 +169,16 @@
     setOperationAction(ISD::BIT_CONVERT      , MVT::i32  , Expand);
   }
 
-  // Scalar integer multiply-high, divide, and remainder are
-  // lowered to use operations that produce two results, to match the
-  // available instructions. This exposes the two-result form to trivial
-  // CSE, which is able to combine x/y and x%y into a single instruction,
-  // for example. The single-result multiply instructions are introduced
-  // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part
-  // is not needed.
+  // Scalar integer divide and remainder are lowered to use operations that
+  // produce two results, to match the available instructions. This exposes
+  // the two-result form to trivial CSE, which is able to combine x/y and x%y
+  // into a single instruction.
+  //
+  // Scalar integer multiply-high is also lowered to use two-result
+  // operations, to match the available instructions. However, plain multiply
+  // (low) operations are left as Legal, as there are single-result
+  // instructions for this in x86. Using the two-result multiply instructions
+  // when both high and low results are needed must be arranged by dagcombine.
   setOperationAction(ISD::MULHS           , MVT::i8    , Expand);
   setOperationAction(ISD::MULHU           , MVT::i8    , Expand);
   setOperationAction(ISD::SDIV            , MVT::i8    , Expand);
@@ -201,11 +204,6 @@
   setOperationAction(ISD::SREM            , MVT::i64   , Expand);
   setOperationAction(ISD::UREM            , MVT::i64   , Expand);
 
-  // 8, 16, and 32-bit plain multiply are legal. And 64-bit multiply
-  // is also legal on x86-64.
-  if (!Subtarget->is64Bit())
-    setOperationAction(ISD::MUL           , MVT::i64   , Expand);
-
   setOperationAction(ISD::BR_JT            , MVT::Other, Expand);
   setOperationAction(ISD::BRCOND           , MVT::Other, Custom);
   setOperationAction(ISD::BR_CC            , MVT::Other, Expand);