[llvm-commits] [llvm] r46866 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll

[Evan Cheng]

Author: evancheng
Date: Thu Feb  7 18:12:56 2008
New Revision: 46866

URL: http://llvm.org/viewvc/llvm-project?rev=46866&view=rev
Log:
Added missing entries in X86 load / store folding tables.

Added:
    llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=46866&r1=46865&r2=46866&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb  7 18:12:56 2008
@@ -495,6 +495,14 @@
     { X86::DIVPSrr,         X86::DIVPSrm },
     { X86::DIVSDrr,         X86::DIVSDrm },
     { X86::DIVSSrr,         X86::DIVSSrm },
+    { X86::FsANDNPDrr,      X86::FsANDNPDrm },
+    { X86::FsANDNPSrr,      X86::FsANDNPSrm },
+    { X86::FsANDPDrr,       X86::FsANDPDrm },
+    { X86::FsANDPSrr,       X86::FsANDPSrm },
+    { X86::FsORPDrr,        X86::FsORPDrm },
+    { X86::FsORPSrr,        X86::FsORPSrm },
+    { X86::FsXORPDrr,       X86::FsXORPDrm },
+    { X86::FsXORPSrr,       X86::FsXORPSrm },
     { X86::HADDPDrr,        X86::HADDPDrm },
     { X86::HADDPSrr,        X86::HADDPSrm },
     { X86::HSUBPDrr,        X86::HSUBPDrm },

Added: llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll?rev=46866&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll Thu Feb  7 18:12:56 2008
@@ -0,0 +1,20 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xor | grep CPI
+
+define void @casin({ double, double }* sret  %agg.result, double %z.0, double %z.1) nounwind  {
+entry:
+	%memtmp = alloca { double, double }, align 8		; <{ double, double }*> [#uses=3]
+	%tmp4 = sub double -0.000000e+00, %z.1		; <double> [#uses=1]
+	call void @casinh( { double, double }* sret  %memtmp, double %tmp4, double %z.0 ) nounwind 
+	%tmp19 = getelementptr { double, double }* %memtmp, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp20 = load double* %tmp19, align 8		; <double> [#uses=1]
+	%tmp22 = getelementptr { double, double }* %memtmp, i32 0, i32 1		; <double*> [#uses=1]
+	%tmp23 = load double* %tmp22, align 8		; <double> [#uses=1]
+	%tmp32 = sub double -0.000000e+00, %tmp20		; <double> [#uses=1]
+	%tmp37 = getelementptr { double, double }* %agg.result, i32 0, i32 0		; <double*> [#uses=1]
+	store double %tmp23, double* %tmp37, align 8
+	%tmp40 = getelementptr { double, double }* %agg.result, i32 0, i32 1		; <double*> [#uses=1]
+	store double %tmp32, double* %tmp40, align 8
+	ret void
+}
+
+declare void @casinh({ double, double }* sret , double, double) nounwind