[llvm-commits] [llvm] r46422 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Author: lattner
Date: Sun Jan 27 17:21:58 2008
New Revision: 46422

URL: http://llvm.org/viewvc/llvm-project?rev=46422&view=rev
Log:
fix a crash on CodeGen/X86/vector-rem.ll

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=46422&r1=46421&r2=46422&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jan 27 17:21:58 2008
@@ -1306,10 +1306,12 @@
     return DAG.getNode(ISD::SREM, VT, N0, N1);
   // If we know the sign bits of both operands are zero, strength reduce to a
   // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
-  uint64_t SignBit = MVT::getIntVTSignBit(VT);
-  if (DAG.MaskedValueIsZero(N1, SignBit) &&
-      DAG.MaskedValueIsZero(N0, SignBit))
-    return DAG.getNode(ISD::UREM, VT, N0, N1);
+  if (!MVT::isVector(VT)) {
+    uint64_t SignBit = MVT::getIntVTSignBit(VT);
+    if (DAG.MaskedValueIsZero(N1, SignBit) &&
+        DAG.MaskedValueIsZero(N0, SignBit))
+      return DAG.getNode(ISD::UREM, VT, N0, N1);
+  }
   
   // If X/C can be simplified by the division-by-constant logic, lower
   // X%C to the equivalent of X-X/C*C.