[llvm-commits] [llvm] r45680 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/X86/

Chris Lattner sabre at nondot.org
Sun Jan 6 19:13:07 PST 2008


Author: lattner
Date: Sun Jan  6 21:13:06 2008
New Revision: 45680

URL: http://llvm.org/viewvc/llvm-project?rev=45680&view=rev
Log:
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/CodeGen/LiveVariables.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/CodeGen/VirtRegMap.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
    llvm/trunk/lib/Target/TargetInstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan  6 21:13:06 2008
@@ -169,8 +169,8 @@
 class TargetInstrDescriptor {
 public:
   unsigned short  Opcode;        // The opcode.
-  unsigned short  numOperands;   // Num of args (may be more if variable_ops).
-  unsigned short  numDefs;       // Num of args that are definitions.
+  unsigned short  NumOperands;   // Num of args (may be more if variable_ops).
+  unsigned short  NumDefs;       // Num of args that are definitions.
   const char *    Name;          // Assembly language mnemonic for the opcode.
   unsigned        SchedClass;    // enum  identifying instr sched class
   unsigned        Flags;         // flags identifying machine instr class
@@ -183,9 +183,9 @@
   /// it is set. Returns -1 if it is not set.
   int getOperandConstraint(unsigned OpNum,
                            TOI::OperandConstraint Constraint) const {
-    assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) &&
+    assert((OpNum < NumOperands || hasVariableOperands()) &&
            "Invalid operand # of TargetInstrInfo");
-    if (OpNum < numOperands &&
+    if (OpNum < NumOperands &&
         (OpInfo[OpNum].Constraints & (1 << Constraint))) {
       unsigned Pos = 16 + Constraint * 4;
       return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
@@ -197,18 +197,50 @@
   /// dest operand. Returns -1 if there isn't one.
   int findTiedToSrcOperand(unsigned OpNum) const;
   
-  bool isCall() const {
-    return Flags & M_CALL_FLAG;
+  const char *getName() const {
+    return Name;
   }
   
-  bool isBranch() const {
-    return Flags & M_BRANCH_FLAG;
+  unsigned getNumOperands() const {
+    return NumOperands;
+  }
+  
+  unsigned getNumDefs() const {
+    return NumDefs;
+  }
+  
+  bool hasVariableOperands() const {
+    return Flags & M_VARIABLE_OPS;
+  }
+  
+  bool hasOptionalDef() const {
+    return Flags & M_HAS_OPTIONAL_DEF;
+  }
+  
+  const unsigned *getImplicitUses() const {
+    return ImplicitUses;
+  }
+  
+  const unsigned *getImplicitDefs() const {
+    return ImplicitDefs;
+  }
+  
+  bool isReturn() const {
+    return Flags & M_RET_FLAG;
+  }
+  
+  bool isCall() const {
+    return Flags & M_CALL_FLAG;
   }
   
   bool isTerminator() const {
     return Flags & M_TERMINATOR_FLAG;
   }
   
+  bool isBranch() const {
+    return Flags & M_BRANCH_FLAG;
+  }
+  
   bool isIndirectBranch() const {
     return Flags & M_INDIRECT_FLAG;
   }
@@ -221,7 +253,16 @@
     return Flags & M_NOT_DUPLICABLE;
   }
   
+  bool isCommutableInstr() const {
+    return Flags & M_COMMUTABLE;
+  }
   
+  /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
+  /// custom insertion support when the DAG scheduler is inserting it into a
+  /// machine basic block.
+  bool usesCustomDAGSchedInsertionHook() const {
+    return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
+  }
   
   /// isSimpleLoad - Return true for instructions that are simple loads from
   /// memory.  This should only be set on instructions that load a value from
@@ -293,54 +334,6 @@
     return desc[Opcode];
   }
 
-  const char *getName(unsigned Opcode) const {
-    return get(Opcode).Name;
-  }
-
-  int getNumOperands(unsigned Opcode) const {
-    return get(Opcode).numOperands;
-  }
-
-  int getNumDefs(unsigned Opcode) const {
-    return get(Opcode).numDefs;
-  }
-
-  const unsigned *getImplicitUses(unsigned Opcode) const {
-    return get(Opcode).ImplicitUses;
-  }
-
-  const unsigned *getImplicitDefs(unsigned Opcode) const {
-    return get(Opcode).ImplicitDefs;
-  }
-
-
-  //
-  // Query instruction class flags according to the machine-independent
-  // flags listed above.
-  //
-  bool isReturn(unsigned Opcode) const {
-    return get(Opcode).Flags & M_RET_FLAG;
-  }
-
-  bool isCommutableInstr(unsigned Opcode) const {
-    return get(Opcode).Flags & M_COMMUTABLE;
-  }
-  
-  /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
-  /// custom insertion support when the DAG scheduler is inserting it into a
-  /// machine basic block.
-  bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
-    return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
-  }
-
-  bool hasVariableOperands(unsigned Opcode) const {
-    return get(Opcode).Flags & M_VARIABLE_OPS;
-  }
-
-  bool hasOptionalDef(unsigned Opcode) const {
-    return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
-  }
-
   /// isTriviallyReMaterializable - Return true if the instruction is trivially
   /// rematerializable, meaning it has no side effects and requires no operands
   /// that aren't always available.

Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Sun Jan  6 21:13:06 2008
@@ -431,7 +431,6 @@
 
 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
   MF = &mf;
-  const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
   RegInfo = MF->getTarget().getRegisterInfo();
   assert(RegInfo && "Target doesn't have register information?");
 
@@ -536,7 +535,7 @@
 
     // Finally, if the last instruction in the block is a return, make sure to mark
     // it as using all of the live-out values in the function.
-    if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
+    if (!MBB->empty() && MBB->back().getDesc()->isReturn()) {
       MachineInstr *Ret = &MBB->back();
       for (MachineRegisterInfo::liveout_iterator
            I = MF->getRegInfo().liveout_begin(),

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sun Jan  6 21:13:06 2008
@@ -252,13 +252,13 @@
 /// instructions with variable number of operands).
 MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
   : TID(&tid), NumImplicitOps(0), Parent(0) {
-  if (!NoImp && TID->ImplicitDefs)
-    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
+  if (!NoImp && TID->getImplicitDefs())
+    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
       NumImplicitOps++;
-  if (!NoImp && TID->ImplicitUses)
-    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
+  if (!NoImp && TID->getImplicitUses())
+    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
       NumImplicitOps++;
-  Operands.reserve(NumImplicitOps + TID->numOperands);
+  Operands.reserve(NumImplicitOps + TID->getNumOperands());
   if (!NoImp)
     addImplicitDefUseOperands();
   // Make sure that we get added to a machine basicblock
@@ -273,12 +273,12 @@
   : TID(&tid), NumImplicitOps(0), Parent(0) {
   assert(MBB && "Cannot use inserting ctor with null basic block!");
   if (TID->ImplicitDefs)
-    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
+    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
       NumImplicitOps++;
   if (TID->ImplicitUses)
-    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
+    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
       NumImplicitOps++;
-  Operands.reserve(NumImplicitOps + TID->numOperands);
+  Operands.reserve(NumImplicitOps + TID->getNumOperands());
   addImplicitDefUseOperands();
   // Make sure that we get added to a machine basicblock
   LeakDetector::addGarbageObject(this);
@@ -487,8 +487,8 @@
 /// OperandComplete - Return true if it's illegal to add a new operand
 ///
 bool MachineInstr::OperandsComplete() const {
-  unsigned short NumOperands = TID->numOperands;
-  if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
+  unsigned short NumOperands = TID->getNumOperands();
+  if (TID->hasVariableOperands() == 0 &&
       getNumOperands()-NumImplicitOps >= NumOperands)
     return true;  // Broken: we have all the operands of this instruction!
   return false;
@@ -497,8 +497,8 @@
 /// getNumExplicitOperands - Returns the number of non-implicit operands.
 ///
 unsigned MachineInstr::getNumExplicitOperands() const {
-  unsigned NumOperands = TID->numOperands;
-  if ((TID->Flags & M_VARIABLE_OPS) == 0)
+  unsigned NumOperands = TID->getNumOperands();
+  if (TID->hasVariableOperands() == 0)
     return NumOperands;
 
   for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Sun Jan  6 21:13:06 2008
@@ -262,7 +262,7 @@
   // Add code to restore the callee-save registers in each exiting block.
   for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
     // If last instruction is a return instruction, add an epilogue.
-    if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
+    if (!FI->empty() && FI->back().getDesc()->isReturn()) {
       MBB = FI;
       I = MBB->end(); --I;
 
@@ -483,10 +483,9 @@
   Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
 
   // Add epilogue to restore the callee-save registers in each exiting block
-  const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
   for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (!I->empty() && TII.isReturn(I->back().getOpcode()))
+    if (!I->empty() && I->back().getDesc()->isReturn())
       Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
   }
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Jan  6 21:13:06 2008
@@ -52,8 +52,8 @@
   unsigned ResNo = Use->getOperand(2).ResNo;
   if (Def->isTargetOpcode()) {
     const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
-    if (ResNo >= II.numDefs &&
-        II.ImplicitDefs[ResNo - II.numDefs] == Reg) {
+    if (ResNo >= II.getNumDefs() &&
+        II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
       PhysReg = Reg;
       const TargetRegisterClass *RC =
         MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
@@ -149,7 +149,7 @@
     if (MainNode->isTargetOpcode()) {
       unsigned Opc = MainNode->getTargetOpcode();
       const TargetInstrDescriptor &TID = TII->get(Opc);
-      for (unsigned i = 0; i != TID.numOperands; ++i) {
+      for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
         if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
           SU->isTwoAddress = true;
           break;
@@ -166,8 +166,8 @@
     for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
       SDNode *N = SU->FlaggedNodes[n];
       if (N->isTargetOpcode() &&
-          TII->getImplicitDefs(N->getTargetOpcode()) &&
-          CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+          TII->get(N->getTargetOpcode()).getImplicitDefs() &&
+          CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
         SU->hasPhysRegDefs = true;
       
       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
@@ -293,7 +293,7 @@
         const TargetInstrInfo *TII,
         const TargetInstrDescriptor *II,
         unsigned Op) {
-  if (Op >= II->numOperands) {
+  if (Op >= II->getNumOperands()) {
     assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
     return NULL;
   }
@@ -373,7 +373,7 @@
                                          MachineInstr *MI,
                                          const TargetInstrDescriptor &II,
                                      DenseMap<SDOperand, unsigned> &VRBaseMap) {
-  for (unsigned i = 0; i < II.numDefs; ++i) {
+  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
     // If the specific node value is only used by a CopyToReg and the dest reg
     // is a vreg, use the CopyToReg'd destination register instead of creating
     // a new vreg.
@@ -435,7 +435,7 @@
     // Get/emit the operand.
     unsigned VReg = getVR(Op, VRBaseMap);
     const TargetInstrDescriptor *TID = MI->getDesc();
-    bool isOptDef = (IIOpNum < TID->numOperands)
+    bool isOptDef = (IIOpNum < TID->getNumOperands())
       ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
     MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
     
@@ -674,10 +674,11 @@
     unsigned NumResults = CountResults(Node);
     unsigned NodeOperands = CountOperands(Node);
     unsigned NumMIOperands = NodeOperands + NumResults;
-    bool     HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs;
+    bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+                          II.getImplicitDefs() != 0;
 #ifndef NDEBUG
-    assert((unsigned(II.numOperands) == NumMIOperands ||
-            HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) &&
+    assert((II.getNumOperands() == NumMIOperands ||
+            HasPhysRegOuts || II.hasVariableOperands()) &&
            "#operands for dag node doesn't match .td file!"); 
 #endif
 
@@ -692,7 +693,7 @@
     // Emit all of the actual operands of this instruction, adding them to the
     // instruction as appropriate.
     for (unsigned i = 0; i != NodeOperands; ++i)
-      AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap);
+      AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
 
     // Commute node if it has been determined to be profitable.
     if (CommuteSet.count(Node)) {
@@ -719,8 +720,8 @@
 
     // Additional results must be an physical register def.
     if (HasPhysRegOuts) {
-      for (unsigned i = II.numDefs; i < NumResults; ++i) {
-        unsigned Reg = II.ImplicitDefs[i - II.numDefs];
+      for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+        unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
         if (Node->hasAnyUseOfValue(i))
           EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sun Jan  6 21:13:06 2008
@@ -148,7 +148,7 @@
     if (!SU || !SU->Node) continue;
     if (SU->isCommutable) {
       unsigned Opc = SU->Node->getTargetOpcode();
-      unsigned NumRes = TII->getNumDefs(Opc);
+      unsigned NumRes = TII->get(Opc).getNumDefs();
       unsigned NumOps = CountOperands(SU->Node);
       for (unsigned j = 0; j != NumOps; ++j) {
         if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
@@ -431,7 +431,7 @@
     SUnit *NewSU = NewSUnit(N);
     SUnitMap[N].push_back(NewSU);
     const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode());
-    for (unsigned i = 0; i != TID->numOperands; ++i) {
+    for (unsigned i = 0; i != TID->getNumOperands(); ++i) {
       if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
         NewSU->isTwoAddress = true;
         break;
@@ -623,8 +623,8 @@
                                             const TargetInstrInfo *TII) {
   const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
   assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
-  unsigned NumRes = TID.numDefs;
-  for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) {
+  unsigned NumRes = TID.getNumDefs();
+  for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
     if (Reg == *ImpDef)
       break;
     ++NumRes;
@@ -1287,7 +1287,7 @@
 bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
   if (SU->isTwoAddress) {
     unsigned Opc = SU->Node->getTargetOpcode();
-    unsigned NumRes = TII->getNumDefs(Opc);
+    unsigned NumRes = TII->get(Opc).getNumDefs();
     unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
     for (unsigned i = 0; i != NumOps; ++i) {
       if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
@@ -1321,11 +1321,12 @@
                                   const TargetInstrInfo *TII,
                                   const MRegisterInfo *MRI) {
   SDNode *N = SuccSU->Node;
-  unsigned NumDefs = TII->getNumDefs(N->getTargetOpcode());
-  const unsigned *ImpDefs = TII->getImplicitDefs(N->getTargetOpcode());
+  unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
+  const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
   if (!ImpDefs)
     return false;
-  const unsigned *SUImpDefs = TII->getImplicitDefs(SU->Node->getTargetOpcode());
+  const unsigned *SUImpDefs =
+    TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
   if (!SUImpDefs)
     return false;
   for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
@@ -1361,7 +1362,7 @@
       continue;
 
     unsigned Opc = Node->getTargetOpcode();
-    unsigned NumRes = TII->getNumDefs(Opc);
+    unsigned NumRes = TII->get(Opc).getNumDefs();
     unsigned NumOps = ScheduleDAG::CountOperands(Node);
     for (unsigned j = 0; j != NumOps; ++j) {
       if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Jan  6 21:13:06 2008
@@ -3602,7 +3602,7 @@
       if (G) {
         if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
           if (getOpcode()-ISD::BUILTIN_OP_END < TII->getNumOpcodes())
-            return TII->getName(getOpcode()-ISD::BUILTIN_OP_END);
+            return TII->get(getOpcode()-ISD::BUILTIN_OP_END).getName();
 
         TargetLowering &TLI = G->getTargetLoweringInfo();
         const char *Name =

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Sun Jan  6 21:13:06 2008
@@ -96,7 +96,7 @@
       const TargetInstrDescriptor *TID = mi->getDesc();
 
       bool FirstTied = true;
-      for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
+      for (unsigned si = 1, e = TID->getNumOperands(); si < e; ++si) {
         int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
         if (ti == -1)
           continue;
@@ -176,7 +176,7 @@
               // FIXME: This assumes there are no more operands which are tied
               // to another register.
 #ifndef NDEBUG
-              for (unsigned i = si+1, e = TID->numOperands; i < e; ++i)
+              for (unsigned i = si+1, e = TID->getNumOperands(); i < e; ++i)
                 assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
 #endif
 

Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Sun Jan  6 21:13:06 2008
@@ -552,7 +552,7 @@
       KillOps[Reg]->setIsKill(false);
       KillOps[Reg] = NULL;
       RegKills.reset(Reg);
-      if (i < TID->numOperands &&
+      if (i < TID->getNumOperands() &&
           TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
         // Unless it's a two-address operand, this is the new kill.
         MO.setIsKill();

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Jan  6 21:13:06 2008
@@ -63,7 +63,7 @@
     return true;
   case ARM::MOVr:
   case ARM::tMOVr:
-    assert(MI.getDesc()->numOperands >= 2 &&
+    assert(MI.getDesc()->getNumOperands() >= 2 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            "Invalid ARM MOV instruction");
@@ -201,7 +201,7 @@
   MachineInstr *MemMI = NULL;
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
   const TargetInstrDescriptor *TID = MI->getDesc();
-  unsigned NumOps = TID->numOperands;
+  unsigned NumOps = TID->getNumOperands();
   bool isLoad = TID->isSimpleLoad();
   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
   const MachineOperand &Base = MI->getOperand(2);
@@ -897,7 +897,7 @@
     case ARM::tBR_JTr: {
       // These are jumptable branches, i.e. a branch followed by an inlined
       // jumptable. The size is 4 + 4 * number of entries.
-      unsigned NumOps = TID->numOperands;
+      unsigned NumOps = TID->getNumOperands();
       MachineOperand JTOP =
         MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
       unsigned JTI = JTOP.getIndex();

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Sun Jan  6 21:13:06 2008
@@ -600,7 +600,7 @@
       unsigned PredReg = 0;
       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
       const TargetInstrDescriptor *TID = MBBI->getDesc();
-      unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
+      unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
       if (isAM2) {

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Sun Jan  6 21:13:06 2008
@@ -261,7 +261,7 @@
       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
       const TargetInstrDescriptor &TID = get(Opc);
 
-      if (TID.numOperands == 3)
+      if (TID.getNumOperands() == 3)
         BuildMI(&MBB, TID).addReg(Cond[1].getReg())
                           .addReg(Cond[2].getReg())
                           .addMBB(TBB);
@@ -277,7 +277,7 @@
   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
   const TargetInstrDescriptor &TID = get(Opc);
 
-  if (TID.numOperands == 3)
+  if (TID.getNumOperands() == 3)
     BuildMI(&MBB, TID).addReg(Cond[1].getReg())
                       .addReg(Cond[2].getReg())
                       .addMBB(TBB);

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sun Jan  6 21:13:06 2008
@@ -262,7 +262,7 @@
   
   // Find all return blocks, outputting a restore in each epilog.
   for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
-    if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
+    if (!BB->empty() && BB->back().getDesc()->isReturn()) {
       IP = BB->end(); --IP;
       
       // Skip over all terminator instructions, which are part of the return

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Jan  6 21:13:06 2008
@@ -538,10 +538,9 @@
   bool RemovedAllMTVRSAVEs = true;
   // See if we can find and remove the MTVRSAVE instruction from all of the
   // epilog blocks.
-  const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
+    if (!I->empty() && I->back().getDesc()->isReturn()) {
       bool FoundIt = false;
       for (MBBI = I->end(); MBBI != I->begin(); ) {
         --MBBI;

Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Sun Jan  6 21:13:06 2008
@@ -19,7 +19,7 @@
 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
 /// dest operand. Returns -1 if there isn't one.
 int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
-  for (unsigned i = 0, e = numOperands; i != e; ++i) {
+  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i == OpNum)
       continue;
     if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Sun Jan  6 21:13:06 2008
@@ -444,7 +444,7 @@
   if (Desc->TSFlags & X86II::REX_W)
     REX |= 1 << 3;
 
-  unsigned NumOps = Desc->numOperands;
+  unsigned NumOps = Desc->getNumOperands();
   if (NumOps) {
     bool isTwoAddr = NumOps > 1 &&
       Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
@@ -584,7 +584,7 @@
     MCE.emitByte(0x0F);
 
   // If this is a two-address instruction, skip one of the register operands.
-  unsigned NumOps = Desc->numOperands;
+  unsigned NumOps = Desc->getNumOperands();
   unsigned CurOp = 0;
   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
     CurOp++;

Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Sun Jan  6 21:13:06 2008
@@ -597,7 +597,7 @@
 ///
 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getDesc()->numOperands;
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   assert((NumOps == 5 || NumOps == 1) &&
          "Can only handle fst* & ftst instructions!");
 
@@ -657,7 +657,7 @@
 ///
 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getDesc()->numOperands;
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
 
   // Is this the last use of the source register?
@@ -766,7 +766,7 @@
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getDesc()->numOperands;
+  unsigned NumOperands = MI->getDesc()->getNumOperands();
   assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
   unsigned Dest = getFPReg(MI->getOperand(0));
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@@ -864,7 +864,7 @@
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getDesc()->numOperands;
+  unsigned NumOperands = MI->getDesc()->getNumOperands();
   assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45680&r1=45679&r2=45680&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Jan  6 21:13:06 2008
@@ -1640,7 +1640,7 @@
     MIB.addImm(1).addReg(0).addImm(0);
   
   // Loop over the rest of the ri operands, converting them over.
-  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
+  unsigned NumOps = MI->getDesc()->getNumOperands()-2;
   for (unsigned i = 0; i != NumOps; ++i) {
     MachineOperand &MO = MI->getOperand(i+2);
     MIB = X86InstrAddOperand(MIB, MO);
@@ -1692,7 +1692,7 @@
                                    SmallVector<MachineOperand,4> &MOs) const {
   const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
   bool isTwoAddrFold = false;
-  unsigned NumOps = getNumOperands(MI->getOpcode());
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   bool isTwoAddr = NumOps > 1 &&
     MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
 
@@ -1798,7 +1798,7 @@
     return NULL;
 
   SmallVector<MachineOperand,4> MOs;
-  unsigned NumOps = getNumOperands(LoadMI->getOpcode());
+  unsigned NumOps = LoadMI->getDesc()->getNumOperands();
   for (unsigned i = NumOps - 4; i != NumOps; ++i)
     MOs.push_back(LoadMI->getOperand(i));
   return foldMemoryOperand(MI, Ops[0], MOs);
@@ -1826,9 +1826,9 @@
 
   unsigned OpNum = Ops[0];
   unsigned Opc = MI->getOpcode();
-  unsigned NumOps = getNumOperands(Opc);
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   bool isTwoAddr = NumOps > 1 &&
-    getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
+    MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
 
   // Folding a memory location into the two-address part of a two-address
   // instruction is different than folding it other places.  It requires
@@ -2011,7 +2011,7 @@
   // Emit the data processing instruction.
   std::vector<MVT::ValueType> VTs;
   const TargetRegisterClass *DstRC = 0;
-  if (TID.numDefs > 0) {
+  if (TID.getNumDefs() > 0) {
     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
     DstRC = DstTOI.isLookupPtrRegClass()
       ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
@@ -2019,7 +2019,7 @@
   }
   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
     MVT::ValueType VT = N->getValueType(i);
-    if (VT != MVT::Other && i >= TID.numDefs)
+    if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
       VTs.push_back(VT);
   }
   if (Load)





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