[llvm-commits] [llvm] r45483 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp

[Chris Lattner]

Author: lattner
Date: Tue Jan  1 15:08:22 2008
New Revision: 45483

URL: http://llvm.org/viewvc/llvm-project?rev=45483&view=rev
Log:
Make MachineRegisterInfo::getVRegDef more efficient by aiming the keep the def of the vreg at the start of the list, so the list doesn't need to be traversed.

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=45483&r1=45482&r2=45483&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Jan  1 15:08:22 2008
@@ -42,17 +42,23 @@
   }
   
   // Otherwise, add this operand to the head of the registers use/def list.
-  MachineOperand *&Head = RegInfo->getRegUseDefListHead(getReg());
+  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
   
-  Contents.Reg.Next = Head;
+  // For SSA values, we prefer to keep the definition at the start of the list.
+  // we do this by skipping over the definition if it is at the head of the
+  // list.
+  if (*Head && (*Head)->isDef())
+    Head = &(*Head)->Contents.Reg.Next;
+  
+  Contents.Reg.Next = *Head;
   if (Contents.Reg.Next) {
     assert(getReg() == Contents.Reg.Next->getReg() &&
            "Different regs on the same list!");
     Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
   }
   
-  Contents.Reg.Prev = &Head;
-  Head = this;
+  Contents.Reg.Prev = Head;
+  *Head = this;
 }
 
 void MachineOperand::setReg(unsigned Reg) {