[llvm-commits] [llvm] r45468 - in /llvm/trunk: docs/CodeGenerator.html lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp

[Chris Lattner]

Author: lattner
Date: Sun Dec 30 22:16:08 2007
New Revision: 45468

URL: http://llvm.org/viewvc/llvm-project?rev=45468&view=rev
Log:
update a couple of references to SSARegMap.

Modified:
    llvm/trunk/docs/CodeGenerator.html
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=45468&r1=45467&r2=45468&view=diff

==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Sun Dec 30 22:16:08 2007
@@ -719,8 +719,7 @@
 corresponds one-to-one with the LLVM function input to the instruction selector.
 In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
 a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
-<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
-live out registers for the function.  See
+<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>.  See
 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
 
 </div>
@@ -1313,8 +1312,8 @@
                                       unsigned p_reg) {
   assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
          "Target register must be physical");
-  const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
-  return trc->contains(p_reg);
+  const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
+  return trc->contains(p_reg);
 }
 </pre>
 </div>
@@ -1343,7 +1342,7 @@
 <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
 application developer, that is not the case with virtual registers.
 In order to create new virtual registers, use the method
-<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
+<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
 virtual register with the highest code.
 </p>
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=45468&r1=45467&r2=45468&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Dec 30 22:16:08 2007
@@ -606,7 +606,7 @@
       SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
     }
     
-    // TODO: Add tracking info to SSARegMap of which vregs are subregs
+    // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
     // to allow coalescing in the allocator
           
     // If the node is only used by a CopyToReg and the dest reg is a vreg, use

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=45468&r1=45467&r2=45468&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sun Dec 30 22:16:08 2007
@@ -1410,8 +1410,8 @@
       (*I)->eraseFromParent();
     }
 
-    // Transfer sub-registers info to SSARegMap now that coalescing information
-    // is complete.
+    // Transfer sub-registers info to MachineRegisterInfo now that coalescing
+    // information is complete.
     RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1);
     while (!SubRegIdxes.empty()) {
       std::pair<unsigned, unsigned> RI = SubRegIdxes.back();