[llvm-commits] [llvm] r45453 - in /llvm/trunk/lib/Target: ./ ARM/ Alpha/ CellSPU/ IA64/ Mips/ PowerPC/ Sparc/ X86/
Chris Lattner
sabre at nondot.org
Sun Dec 30 12:49:50 PST 2007
Author: lattner
Date: Sun Dec 30 14:49:49 2007
New Revision: 45453
URL: http://llvm.org/viewvc/llvm-project?rev=45453&view=rev
Log:
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp
llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp
llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp
llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp
llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/trunk/lib/Target/TargetInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86AsmPrinter.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -271,7 +271,7 @@
if (!Modifier || strcmp(Modifier, "no_hash") != 0)
O << "#";
- O << (int)MO.getImmedValue();
+ O << (int)MO.getImm();
break;
}
case MachineOperand::MO_MachineBasicBlock:
@@ -351,7 +351,7 @@
void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!");
- printSOImm(O, MO.getImmedValue(), TAI);
+ printSOImm(O, MO.getImm(), TAI);
}
/// printSOImm2PartOperand - SOImm is broken into two pieces using a mov
@@ -359,8 +359,8 @@
void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!");
- unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImmedValue());
- unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImmedValue());
+ unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
+ unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
O << "\n\torr";
printPredicateOperand(MI, 2);
@@ -387,7 +387,7 @@
// Print the shift opc.
O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImmedValue()))
+ << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
<< " ";
if (MO2.getReg()) {
@@ -426,7 +426,7 @@
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImmedValue()))
+ << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
<< " #" << ShImm;
O << "]";
}
@@ -449,7 +449,7 @@
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImmedValue()))
+ << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
<< " #" << ShImm;
}
@@ -617,7 +617,7 @@
}
void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
- ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImmedValue();
+ ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImm();
if (CC != ARMCC::AL)
O << ARMCondCodeToString(CC);
}
@@ -631,7 +631,7 @@
}
void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int opNum) {
- int Id = (int)MI->getOperand(opNum).getImmedValue();
+ int Id = (int)MI->getOperand(opNum).getImm();
O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
}
@@ -677,7 +677,7 @@
const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
unsigned JTI = MO1.getJumpTableIndex();
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
- << '_' << JTI << '_' << MO2.getImmedValue() << ":\n";
+ << '_' << JTI << '_' << MO2.getImm() << ":\n";
const char *JTEntryDirective = TAI->getJumpTableDirective();
if (!JTEntryDirective)
@@ -692,19 +692,19 @@
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
MachineBasicBlock *MBB = JTBBs[i];
if (UseSet && JTSets.insert(MBB).second)
- printPICJumpTableSetLabel(JTI, MO2.getImmedValue(), MBB);
+ printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
O << JTEntryDirective << ' ';
if (UseSet)
O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
- << '_' << JTI << '_' << MO2.getImmedValue()
+ << '_' << JTI << '_' << MO2.getImm()
<< "_set_" << MBB->getNumber();
else if (TM.getRelocationModel() == Reloc::PIC_) {
printBasicBlockLabel(MBB, false, false);
// If the arch uses custom Jump Table directives, don't calc relative to JT
if (!TAI->getJumpTableDirective())
O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
- << getFunctionNumber() << '_' << JTI << '_' << MO2.getImmedValue();
+ << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
} else
printBasicBlockLabel(MBB, false, false);
if (i != e-1)
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Sun Dec 30 14:49:49 2007
@@ -111,7 +111,7 @@
/// machine operand.
int Emitter::getShiftOp(const MachineOperand &MO) {
unsigned ShiftOp = 0x0;
- switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
+ switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr:
ShiftOp = 0X2;
@@ -137,7 +137,7 @@
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
} else if (MO.isImmediate()) {
- rv = MO.getImmedValue();
+ rv = MO.getImm();
} else if (MO.isGlobalAddress()) {
emitGlobalAddressForCall(MO.getGlobal(), false);
} else if (MO.isExternalSymbol()) {
@@ -412,7 +412,7 @@
Value |= 1 << ARMII::I_BitShift;
// set immed_8 field
const MachineOperand &MO = MI.getOperand(OperandIndex);
- op = ARM_AM::getSOImmVal(MO.getImmedValue());
+ op = ARM_AM::getSOImmVal(MO.getImm());
Value |= op;
break;
@@ -441,7 +441,7 @@
// LSR - 011 if it is in register shifts encoding; 010, otherwise.
// ROR - 111 if it is in register shifts encoding; 110, otherwise.
// RRX - 110 and bit[11:7] clear.
- switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
+ switch(ARM_AM::getSORegShOp(MO2.getImm())) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr: {
if(IsShiftByRegister)
@@ -475,7 +475,7 @@
}
}
// set the field related to shift operations (except rrx).
- if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
+ if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
if(IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Sun Dec 30 14:49:49 2007
@@ -1188,7 +1188,7 @@
// bge L2
// b L1
// L2:
- ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
+ ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
CC = ARMCC::getOppositeCondition(CC);
unsigned CCReg = MI->getOperand(2).getReg();
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -70,7 +70,7 @@
MI->getOperand(2).isRegister() &&
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
- MI->getOperand(3).getImmedValue() == 0) {
+ MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -79,7 +79,7 @@
case ARM::FLDS:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -87,7 +87,7 @@
case ARM::tRestore:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -104,7 +104,7 @@
MI->getOperand(2).isRegister() &&
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
- MI->getOperand(3).getImmedValue() == 0) {
+ MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -113,7 +113,7 @@
case ARM::FSTS:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -121,7 +121,7 @@
case ARM::tSpill:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -461,7 +461,7 @@
bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
- return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
+ return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
}
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
@@ -477,7 +477,7 @@
int PIdx = MI->findFirstPredOperandIdx();
if (PIdx != -1) {
MachineOperand &PMO = MI->getOperand(PIdx);
- PMO.setImm(Pred[0].getImmedValue());
+ PMO.setImm(Pred[0].getImm());
MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
return true;
}
@@ -490,8 +490,8 @@
if (Pred1.size() > 2 || Pred2.size() > 2)
return false;
- ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
- ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
+ ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
+ ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
if (CC1 == CC2)
return true;
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Sun Dec 30 14:49:49 2007
@@ -255,7 +255,7 @@
}
PredReg = MI->getOperand(PIdx+1).getReg();
- return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
+ return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
}
static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -321,8 +321,8 @@
const MachineInstr *Orig) const {
if (Orig->getOpcode() == ARM::MOVi2pieces) {
emitLoadConstPool(MBB, I, DestReg,
- Orig->getOperand(1).getImmedValue(),
- (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
+ Orig->getOperand(1).getImm(),
+ (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
Orig->getOperand(3).getReg(),
TII, false);
return;
@@ -360,7 +360,7 @@
if (MI->getOperand(4).getReg() == ARM::CPSR)
// If it is updating CPSR, then it cannot be foled.
break;
- unsigned Pred = MI->getOperand(2).getImmedValue();
+ unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@@ -392,7 +392,7 @@
break;
}
case ARM::FCPYS: {
- unsigned Pred = MI->getOperand(2).getImmedValue();
+ unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@@ -406,7 +406,7 @@
break;
}
case ARM::FCPYD: {
- unsigned Pred = MI->getOperand(2).getImmedValue();
+ unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@@ -792,7 +792,7 @@
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
// ADJCALLSTACKUP -> add, sp, sp, amount
MachineInstr *Old = I;
- unsigned Amount = Old->getOperand(0).getImmedValue();
+ unsigned Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
// We need to keep the stack aligned properly. To do this, we round the
@@ -805,7 +805,7 @@
unsigned Opc = Old->getOpcode();
bool isThumb = AFI->isThumbFunction();
ARMCC::CondCodes Pred = isThumb
- ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
+ ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
@@ -1160,7 +1160,7 @@
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
- ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
+ ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, Pred, PredReg, TII);
Modified: llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -78,8 +78,8 @@
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
- O << MO.getImmedValue();
- assert(MO.getImmedValue() < (1 << 30));
+ O << MO.getImm();
+ assert(MO.getImm() < (1 << 30));
} else {
printOp(MO);
}
Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Sun Dec 30 14:49:49 2007
@@ -151,7 +151,7 @@
if (MO.isRegister()) {
rv = getAlphaRegNumber(MO.getReg());
} else if (MO.isImmediate()) {
- rv = MO.getImmedValue();
+ rv = MO.getImm();
} else if (MO.isGlobalAddress() || MO.isExternalSymbol()
|| MO.isConstantPoolIndex()) {
DOUT << MO << " is a relocated op for " << MI << "\n";
@@ -187,7 +187,7 @@
case Alpha::LDAg:
case Alpha::LDAHg:
Reloc = Alpha::reloc_gpdist;
- Offset = MI.getOperand(3).getImmedValue();
+ Offset = MI.getOperand(3).getImm();
break;
default:
assert(0 && "unknown relocatable instruction");
@@ -195,12 +195,12 @@
}
if (MO.isGlobalAddress())
MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- Reloc, MO.getGlobal(), Offset,
- false, useGOT));
+ Reloc, MO.getGlobal(), Offset,
+ false, useGOT));
else if (MO.isExternalSymbol())
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
- Reloc, MO.getSymbolName(), Offset,
- true));
+ Reloc, MO.getSymbolName(),
+ Offset, true));
else
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, MO.getConstantPoolIndex(),
Modified: llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaLLRP.cpp Sun Dec 30 14:49:49 2007
@@ -67,11 +67,9 @@
case Alpha::STW: case Alpha::STB:
case Alpha::STT: case Alpha::STS:
if (MI->getOperand(2).getReg() == Alpha::R30) {
- if (prev[0]
- && prev[0]->getOperand(2).getReg() ==
- MI->getOperand(2).getReg()
- && prev[0]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
+ if (prev[0] &&
+ prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
+ prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
prev[0] = prev[1];
prev[1] = prev[2];
prev[2] = 0;
@@ -83,8 +81,8 @@
} else if (prev[1]
&& prev[1]->getOperand(2).getReg() ==
MI->getOperand(2).getReg()
- && prev[1]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
+ && prev[1]->getOperand(1).getImm() ==
+ MI->getOperand(1).getImm()) {
prev[0] = prev[2];
prev[1] = prev[2] = 0;
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
@@ -98,8 +96,8 @@
} else if (prev[2]
&& prev[2]->getOperand(2).getReg() ==
MI->getOperand(2).getReg()
- && prev[2]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
+ && prev[2]->getOperand(1).getImm() ==
+ MI->getOperand(1).getImm()) {
prev[0] = prev[1] = prev[2] = 0;
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -280,7 +280,7 @@
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
// <amt>'
MachineInstr *Old = I;
- uint64_t Amount = Old->getOperand(0).getImmedValue();
+ uint64_t Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
Modified: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -83,7 +83,7 @@
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
- O << MO.getImmedValue();
+ O << MO.getImm();
} else {
printOp(MO);
}
@@ -98,7 +98,7 @@
void
printS7ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- int value = MI->getOperand(OpNo).getImmedValue();
+ int value = MI->getOperand(OpNo).getImm();
value = (value << (32 - 7)) >> (32 - 7);
assert((value >= -(1 << 8) && value <= (1 << 7) - 1)
@@ -109,7 +109,7 @@
void
printU7ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- unsigned int value = MI->getOperand(OpNo).getImmedValue();
+ unsigned int value = MI->getOperand(OpNo).getImm();
assert(value < (1 << 8) && "Invalid u7 argument");
O << value;
}
@@ -117,7 +117,7 @@
void
printMemRegImmS7(const MachineInstr *MI, unsigned OpNo)
{
- char value = MI->getOperand(OpNo).getImmedValue();
+ char value = MI->getOperand(OpNo).getImm();
O << (int) value;
O << "(";
printOperand(MI, OpNo+1);
@@ -127,19 +127,19 @@
void
printS16ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- O << (short) MI->getOperand(OpNo).getImmedValue();
+ O << (short) MI->getOperand(OpNo).getImm();
}
void
printU16ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
+ O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void
printU32ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- O << (unsigned)MI->getOperand(OpNo).getImmedValue();
+ O << (unsigned)MI->getOperand(OpNo).getImm();
}
void
@@ -156,7 +156,7 @@
void
printU18ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- unsigned int value = MI->getOperand(OpNo).getImmedValue();
+ unsigned int value = MI->getOperand(OpNo).getImm();
assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
O << value;
}
@@ -164,7 +164,7 @@
void
printS10ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
+ short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
assert((value >= -(1 << 9) && value <= (1 << 9) - 1)
&& "Invalid s10 argument");
@@ -174,7 +174,7 @@
void
printU10ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
- short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
+ short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
assert((value <= (1 << 10) - 1) && "Invalid u10 argument");
O << value;
@@ -238,23 +238,23 @@
void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
- int value = (int) MI->getOperand(OpNo).getImmedValue();
+ int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 16)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
- int value = (int) MI->getOperand(OpNo).getImmedValue();
+ int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 32)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -64,7 +64,7 @@
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
- if (MI.getOperand(2).getImmedValue() == 0) {
+ if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -77,7 +77,7 @@
(MI.getOperand(1).isRegister() ||
MI.getOperand(1).isFrameIndex()) &&
(MI.getOperand(2).isImmediate() &&
- MI.getOperand(2).getImmedValue() == 0)) {
+ MI.getOperand(2).getImm() == 0)) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -137,7 +137,7 @@
case SPU::LQXr64:
case SPU::LQXr32:
case SPU::LQXr16:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@@ -171,7 +171,7 @@
case SPU::STQXr32:
case SPU::STQXr16:
// case SPU::STQXr8:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -263,11 +263,11 @@
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
- MIB.addReg(MO.getReg());
+ MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
- MIB.addFrameIndex(MO.getFrameIndex());
+ MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
}
@@ -349,11 +349,11 @@
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
- MIB.addReg(MO.getReg());
+ MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
- MIB.addFrameIndex(MO.getFrameIndex());
+ MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
}
@@ -610,10 +610,9 @@
MachineOperand &MO = MI.getOperand(OpNo);
// Offset is biased by $lr's slot at the bottom.
- Offset += MO.getImmedValue() + MFI->getStackSize()
- + SPUFrameInfo::minStackSize();
+ Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
assert((Offset & 0xf) == 0
- && "16-byte alignment violated in SPURegisterInfo::eliminateFrameIndex");
+ && "16-byte alignment violated in eliminateFrameIndex");
// Replace the FrameIndex with base register with $sp (aka $r1)
SPOp.ChangeToRegister(SPU::R1, false);
Modified: llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -62,22 +62,22 @@
}
void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
+ int val=(unsigned int)MI->getOperand(OpNo).getImm();
if(val>=128) val=val-256; // if negative, flip sign
O << val;
}
void printS14ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
+ int val=(unsigned int)MI->getOperand(OpNo).getImm();
if(val>=8192) val=val-16384; // if negative, flip sign
O << val;
}
void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
+ int val=(unsigned int)MI->getOperand(OpNo).getImm();
if(val>=2097152) val=val-4194304; // if negative, flip sign
O << val;
}
void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- O << (uint64_t)MI->getOperand(OpNo).getImmedValue();
+ O << (uint64_t)MI->getOperand(OpNo).getImm();
}
void printS64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
// XXX : nasty hack to avoid GPREL22 "relocation truncated to fit" linker
@@ -90,7 +90,7 @@
// If it's an immediate, print it the old fashioned way. If it's
// not, we print it as a constant pool index.
if(MI->getOperand(OpNo).isImmediate()) {
- O << (int64_t)MI->getOperand(OpNo).getImmedValue();
+ O << (int64_t)MI->getOperand(OpNo).getImm();
} else { // this is a constant pool reference: FIXME: assert this
printOp(MI->getOperand(OpNo));
}
@@ -172,7 +172,7 @@
return;
case MachineOperand::MO_Immediate:
- O << MO.getImmedValue();
+ O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -84,7 +84,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -136,7 +136,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -220,7 +220,7 @@
// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
// <amt>'
MachineInstr *Old = I;
- unsigned Amount = Old->getOperand(0).getImmedValue();
+ unsigned Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -374,9 +374,9 @@
case MachineOperand::MO_Immediate:
if ((MI->getOpcode() == Mips::SLTiu) || (MI->getOpcode() == Mips::ORi) ||
(MI->getOpcode() == Mips::LUi) || (MI->getOpcode() == Mips::ANDi))
- O << (unsigned short int)MO.getImmedValue();
+ O << (unsigned short int)MO.getImm();
else
- O << (short int)MO.getImmedValue();
+ O << (short int)MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -25,7 +25,7 @@
TM(tm), RI(*this) {}
static bool isZeroImm(const MachineOperand &op) {
- return op.isImmediate() && op.getImmedValue() == 0;
+ return op.isImmediate() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -109,7 +109,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -140,7 +140,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -124,7 +124,7 @@
if (MO.isRegister()) {
printRegister(MO, false);
} else if (MO.isImmediate()) {
- O << MO.getImmedValue();
+ O << MO.getImm();
} else {
printOp(MO);
}
@@ -137,29 +137,29 @@
void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- char value = MI->getOperand(OpNo).getImmedValue();
+ char value = MI->getOperand(OpNo).getImm();
value = (value << (32-5)) >> (32-5);
O << (int)value;
}
void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- unsigned char value = MI->getOperand(OpNo).getImmedValue();
+ unsigned char value = MI->getOperand(OpNo).getImm();
assert(value <= 31 && "Invalid u5imm argument!");
O << (unsigned int)value;
}
void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- unsigned char value = MI->getOperand(OpNo).getImmedValue();
+ unsigned char value = MI->getOperand(OpNo).getImm();
assert(value <= 63 && "Invalid u6imm argument!");
O << (unsigned int)value;
}
void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- O << (short)MI->getOperand(OpNo).getImmedValue();
+ O << (short)MI->getOperand(OpNo).getImm();
}
void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
+ O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
- O << (short)(MI->getOperand(OpNo).getImmedValue()*4);
+ O << (short)(MI->getOperand(OpNo).getImm()*4);
} else {
O << "lo16(";
printOp(MI->getOperand(OpNo));
@@ -173,7 +173,7 @@
// Branches can take an immediate operand. This is used by the branch
// selection pass to print $+8, an eight byte displacement from the PC.
if (MI->getOperand(OpNo).isImmediate()) {
- O << "$+" << MI->getOperand(OpNo).getImmedValue()*4;
+ O << "$+" << MI->getOperand(OpNo).getImm()*4;
} else {
printOp(MI->getOperand(OpNo));
}
@@ -205,7 +205,7 @@
printOp(MI->getOperand(OpNo));
}
void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo) {
- O << (int)MI->getOperand(OpNo).getImmedValue()*4;
+ O << (int)MI->getOperand(OpNo).getImm()*4;
}
void printPICLabel(const MachineInstr *MI, unsigned OpNo) {
O << "\"L" << getFunctionNumber() << "$pb\"\n";
@@ -509,9 +509,9 @@
// Check for slwi/srwi mnemonics.
if (MI->getOpcode() == PPC::RLWINM) {
bool FoundMnemonic = false;
- unsigned char SH = MI->getOperand(2).getImmedValue();
- unsigned char MB = MI->getOperand(3).getImmedValue();
- unsigned char ME = MI->getOperand(4).getImmedValue();
+ unsigned char SH = MI->getOperand(2).getImm();
+ unsigned char MB = MI->getOperand(3).getImm();
+ unsigned char ME = MI->getOperand(4).getImm();
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
O << "slwi "; FoundMnemonic = true;
}
@@ -536,8 +536,8 @@
return;
}
} else if (MI->getOpcode() == PPC::RLDICR) {
- unsigned char SH = MI->getOperand(2).getImmedValue();
- unsigned char ME = MI->getOperand(3).getImmedValue();
+ unsigned char SH = MI->getOperand(2).getImm();
+ unsigned char ME = MI->getOperand(3).getImm();
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) {
O << "sldi ";
Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Sun Dec 30 14:49:49 2007
@@ -131,7 +131,7 @@
rv = 0x80 >> rv;
}
} else if (MO.isImmediate()) {
- rv = MO.getImmedValue();
+ rv = MO.getImm();
} else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
unsigned Reloc = 0;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -54,7 +54,7 @@
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ADDI instruction!");
- if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
+ if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -65,7 +65,7 @@
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ORI instruction!");
- if (MI.getOperand(2).getImmedValue()==0) {
+ if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -99,7 +99,7 @@
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@@ -117,7 +117,7 @@
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@@ -135,7 +135,7 @@
return TargetInstrInfo::commuteInstruction(MI);
// Cannot commute if it has a non-zero rotate count.
- if (MI->getOperand(3).getImmedValue() != 0)
+ if (MI->getOperand(3).getImm() != 0)
return 0;
// If we have a zero rotate count, we have:
@@ -162,10 +162,10 @@
MI->getOperand(1).unsetIsKill();
// Swap the mask around.
- unsigned MB = MI->getOperand(4).getImmedValue();
- unsigned ME = MI->getOperand(5).getImmedValue();
- MI->getOperand(4).setImmedValue((ME+1) & 31);
- MI->getOperand(5).setImmedValue((MB-1) & 31);
+ unsigned MB = MI->getOperand(4).getImm();
+ unsigned ME = MI->getOperand(5).getImm();
+ MI->getOperand(4).setImm((ME+1) & 31);
+ MI->getOperand(5).setImm((MB-1) & 31);
return MI;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -214,7 +214,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -324,7 +324,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -802,9 +802,9 @@
// Now add the frame object offset to the offset from r1.
int Offset = MFI->getObjectOffset(FrameIndex);
if (!isIXAddr)
- Offset += MI.getOperand(OffsetOperandNo).getImmedValue();
+ Offset += MI.getOperand(OffsetOperandNo).getImm();
else
- Offset += MI.getOperand(OffsetOperandNo).getImmedValue() << 2;
+ Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
// If we're not using a Frame Pointer that has been set to the value of the
// SP before having the stack size subtracted from it, then add the stack size
Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -152,7 +152,7 @@
break;
case MachineOperand::MO_Immediate:
- O << (int)MO.getImmedValue();
+ O << (int)MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
@@ -188,7 +188,7 @@
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if (MI->getOperand(opNum+1).isImmediate() &&
- MI->getOperand(opNum+1).getImmedValue() == 0)
+ MI->getOperand(opNum+1).getImm() == 0)
return; // don't print "+0"
O << "+";
@@ -203,7 +203,7 @@
}
void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
- int CC = (int)MI->getOperand(opNum).getImmedValue();
+ int CC = (int)MI->getOperand(opNum).getImm();
O << SPARCCondCodeToString((SPCC::CondCodes)CC);
}
Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sun Dec 30 14:49:49 2007
@@ -912,7 +912,7 @@
break;
}
- CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
+ CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -24,7 +24,7 @@
}
static bool isZeroImm(const MachineOperand &op) {
- return op.isImmediate() && op.getImmedValue() == 0;
+ return op.isImmediate() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
@@ -71,7 +71,7 @@
MI->getOpcode() == SP::LDFri ||
MI->getOpcode() == SP::LDDFri) {
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 0) {
+ MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -90,7 +90,7 @@
MI->getOpcode() == SP::STFri ||
MI->getOpcode() == SP::STDFri) {
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
- MI->getOperand(1).getImmedValue() == 0) {
+ MI->getOperand(1).getImm() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();
return MI->getOperand(2).getReg();
}
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Sun Dec 30 14:49:49 2007
@@ -68,7 +68,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -110,7 +110,7 @@
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
- MIB.addImm(MO.getImmedValue());
+ MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@@ -222,7 +222,7 @@
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
MachineInstr &MI = *I;
- int Size = MI.getOperand(0).getImmedValue();
+ int Size = MI.getOperand(0).getImm();
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
@@ -246,7 +246,7 @@
// Addressable stack objects are accessed using neg. offsets from %fp
MachineFunction &MF = *MI.getParent()->getParent();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
- MI.getOperand(i+1).getImmedValue();
+ MI.getOperand(i+1).getImm();
// Replace frame index with a frame pointer reference.
if (Offset >= -4096 && Offset <= 4095) {
Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -72,7 +72,7 @@
MO.setReg(Pred[j].getReg());
MadeChange = true;
} else if (MO.isImmediate()) {
- MO.setImm(Pred[j].getImmedValue());
+ MO.setImm(Pred[j].getImm());
MadeChange = true;
} else if (MO.isMachineBasicBlock()) {
MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -229,7 +229,7 @@
if (!Modifier ||
(strcmp(Modifier, "debug") && strcmp(Modifier, "mem")))
O << '$';
- O << MO.getImmedValue();
+ O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
@@ -440,7 +440,7 @@
}
void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
- unsigned char value = MI->getOperand(Op).getImmedValue();
+ unsigned char value = MI->getOperand(Op).getImm();
assert(value <= 7 && "Invalid ssecc argument!");
switch (value) {
case 0: O << "eq"; break;
@@ -467,13 +467,13 @@
DispSpec.isJumpTableIndex()) {
printOperand(MI, Op+3, "mem", NotRIPRel);
} else {
- int DispVal = DispSpec.getImmedValue();
+ int DispVal = DispSpec.getImm();
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
O << DispVal;
}
if (IndexReg.getReg() || BaseReg.getReg()) {
- unsigned ScaleVal = MI->getOperand(Op+1).getImmedValue();
+ unsigned ScaleVal = MI->getOperand(Op+1).getImm();
unsigned BaseRegOperand = 0, IndexRegOperand = 2;
// There are cases where we can end up with ESP/RSP in the indexreg slot.
Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.h?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/X86/X86AsmPrinter.h Sun Dec 30 14:49:49 2007
@@ -77,8 +77,8 @@
inline static bool isScale(const MachineOperand &MO) {
return MO.isImmediate() &&
- (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
- MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
+ (MO.getImm() == 1 || MO.getImm() == 2 ||
+ MO.getImm() == 4 || MO.getImm() == 8);
}
inline static bool isMem(const MachineInstr *MI, unsigned Op) {
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Dec 30 14:49:49 2007
@@ -73,9 +73,9 @@
case X86::MMX_MOVQ64rm:
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 1 &&
+ MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0 &&
- MI->getOperand(4).getImmedValue() == 0) {
+ MI->getOperand(4).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@@ -104,9 +104,9 @@
case X86::MMX_MOVNTQmr:
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
- MI->getOperand(1).getImmedValue() == 1 &&
+ MI->getOperand(1).getImm() == 1 &&
MI->getOperand(2).getReg() == 0 &&
- MI->getOperand(3).getImmedValue() == 0) {
+ MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();
return MI->getOperand(4).getReg();
}
@@ -136,7 +136,7 @@
return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 &&
- MI->getOperand(2).getImmedValue() == 1 &&
+ MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0;
}
// All other instructions marked M_REMATERIALIZABLE are always trivially
@@ -194,7 +194,7 @@
MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() &&
MI->getOperand(4).isGlobalAddress() &&
- MI->getOperand(2).getImmedValue() == 1 &&
+ MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0)
return true;
}
@@ -217,7 +217,7 @@
MI->getOperand(3).isRegister() &&
MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 &&
- MI->getOperand(2).getImmedValue() == 1 &&
+ MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0;
}
@@ -404,7 +404,7 @@
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
- MI->getOperand(2).getImmedValue());
+ MI->getOperand(2).getImm());
break;
case X86::ADD32ri:
case X86::ADD32ri8:
@@ -412,7 +412,7 @@
if (MI->getOperand(2).isImmediate()) {
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
- MI->getOperand(2).getImmedValue());
+ MI->getOperand(2).getImm());
}
break;
case X86::ADD16ri:
@@ -421,7 +421,7 @@
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
- MI->getOperand(2).getImmedValue());
+ MI->getOperand(2).getImm());
break;
case X86::SHL16ri:
if (DisableLEA16) return 0;
@@ -429,7 +429,7 @@
case X86::SHL64ri: {
assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
"Unknown shl instruction!");
- unsigned ShAmt = MI->getOperand(2).getImmedValue();
+ unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
X86AddressMode AM;
AM.Scale = 1 << ShAmt;
@@ -473,7 +473,7 @@
case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
}
- unsigned Amt = MI->getOperand(3).getImmedValue();
+ unsigned Amt = MI->getOperand(3).getImm();
unsigned A = MI->getOperand(0).getReg();
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();
Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp?rev=45453&r1=45452&r2=45453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp Sun Dec 30 14:49:49 2007
@@ -99,7 +99,7 @@
}
void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
- unsigned char value = MI->getOperand(Op).getImmedValue();
+ unsigned char value = MI->getOperand(Op).getImm();
assert(value <= 7 && "Invalid ssecc argument!");
switch (value) {
case 0: O << "eq"; break;
@@ -132,7 +132,7 @@
return;
}
case MachineOperand::MO_Immediate:
- O << MO.getImmedValue();
+ O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
@@ -195,7 +195,7 @@
assert(isMem(MI, Op) && "Invalid memory reference!");
const MachineOperand &BaseReg = MI->getOperand(Op);
- int ScaleVal = MI->getOperand(Op+1).getImmedValue();
+ int ScaleVal = MI->getOperand(Op+1).getImm();
const MachineOperand &IndexReg = MI->getOperand(Op+2);
const MachineOperand &DispSpec = MI->getOperand(Op+3);
@@ -220,7 +220,7 @@
O << " + ";
printOp(DispSpec, "mem");
} else {
- int DispVal = DispSpec.getImmedValue();
+ int DispVal = DispSpec.getImm();
if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
if (NeedPlus)
if (DispVal > 0)
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