[llvm-commits] [llvm] r45437 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.cpp ARMRegisterInfo.cpp

[Chris Lattner]

Author: lattner
Date: Sat Dec 29 19:01:54 2007
New Revision: 45437

URL: http://llvm.org/viewvc/llvm-project?rev=45437&view=rev
Log:
use simplified operand addition methods.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45437&r1=45436&r2=45437&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sat Dec 29 19:01:54 2007
@@ -469,8 +469,8 @@
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
-    MI->addImmOperand(Pred[0].getImmedValue());
-    MI->addRegOperand(Pred[1].getReg(), false);
+    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
+    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
     return true;
   }
 

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=45437&r1=45436&r2=45437&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Sat Dec 29 19:01:54 2007
@@ -126,7 +126,7 @@
       PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
       MBB.erase(MI);
     }
-    PopMI->addRegOperand(Reg, true);
+    PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
   }
   return true;
 }
@@ -1100,9 +1100,10 @@
       MI.setInstrDescriptor(TII.get(ARM::tLDR));
       MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
       if (UseRR)
-        MI.addRegOperand(FrameReg, false);  // Use [reg, reg] addrmode.
-      else
-        MI.addRegOperand(0, false); // tLDR has an extra register operand.
+        // Use [reg, reg] addrmode.
+        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
+      else  // tLDR has an extra register operand.
+        MI.addOperand(MachineOperand::CreateReg(0, false));
     } else if (TII.isStore(Opcode)) {
       // FIXME! This is horrific!!! We need register scavenging.
       // Our temporary workaround has marked r3 unavailable. Of course, r3 is
@@ -1134,10 +1135,10 @@
         emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
       MI.setInstrDescriptor(TII.get(ARM::tSTR));
       MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
-      if (UseRR)
-        MI.addRegOperand(FrameReg, false);  // Use [reg, reg] addrmode.
-      else
-        MI.addRegOperand(0, false); // tSTR has an extra register operand.
+      if (UseRR)  // Use [reg, reg] addrmode.
+        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
+      else // tSTR has an extra register operand.
+        MI.addOperand(MachineOperand::CreateReg(0, false));
 
       MachineBasicBlock::iterator NII = next(II);
       if (ValReg == ARM::R3)