[llvm-commits] [llvm] r44954 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_ctbits.ll

[Dan Gohman]

Author: djg
Date: Wed Dec 12 16:21:26 2007
New Revision: 44954

URL: http://llvm.org/viewvc/llvm-project?rev=44954&view=rev
Log:
Allow vector integer constants to be created with
SelectionDAG::getConstant, in the same way as vector floating-point
constants. This allows the legalize expansion code for @llvm.ctpop and
friends to be usable with vector types.

Added:
    llvm/trunk/test/CodeGen/X86/vec_ctbits.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=44954&r1=44953&r2=44954&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Dec 12 16:21:26 2007
@@ -687,22 +687,35 @@
 
 SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) {
   assert(MVT::isInteger(VT) && "Cannot create FP integer constant!");
-  assert(!MVT::isVector(VT) && "Cannot create Vector ConstantSDNodes!");
+
+  MVT::ValueType EltVT =
+    MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
   
   // Mask out any bits that are not valid for this constant.
-  Val &= MVT::getIntVTBitMask(VT);
+  Val &= MVT::getIntVTBitMask(EltVT);
 
   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
   FoldingSetNodeID ID;
-  AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
+  AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
   ID.AddInteger(Val);
   void *IP = 0;
-  if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
-    return SDOperand(E, 0);
-  SDNode *N = new ConstantSDNode(isT, Val, VT);
-  CSEMap.InsertNode(N, IP);
-  AllNodes.push_back(N);
-  return SDOperand(N, 0);
+  SDNode *N = NULL;
+  if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
+    if (!MVT::isVector(VT))
+      return SDOperand(N, 0);
+  if (!N) {
+    N = new ConstantSDNode(isT, Val, EltVT);
+    CSEMap.InsertNode(N, IP);
+    AllNodes.push_back(N);
+  }
+
+  SDOperand Result(N, 0);
+  if (MVT::isVector(VT)) {
+    SmallVector<SDOperand, 8> Ops;
+    Ops.assign(MVT::getVectorNumElements(VT), Result);
+    Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
+  }
+  return Result;
 }
 
 SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT,

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=44954&r1=44953&r2=44954&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 12 16:21:26 2007
@@ -483,6 +483,12 @@
     setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
     setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
+    setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
   }
 
   if (Subtarget->hasMMX()) {

Added: llvm/trunk/test/CodeGen/X86/vec_ctbits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ctbits.ll?rev=44954&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_ctbits.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_ctbits.ll Wed Dec 12 16:21:26 2007
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | llc -march=x86-64
+
+declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>)
+declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>)
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
+
+define <2 x i64> @footz(<2 x i64> %a) {
+  %c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a)
+  ret <2 x i64> %c
+}
+define <2 x i64> @foolz(<2 x i64> %a) {
+  %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a)
+  ret <2 x i64> %c
+}
+define <2 x i64> @foopop(<2 x i64> %a) {
+  %c = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
+  ret <2 x i64> %c
+}