[llvm-commits] [llvm] r44874 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp

[Evan Cheng]

vreg definition info is trivial but there is no reverse link from  
vreg to defining MachineInstruction. That's what  
MachineLICM::MapVirtualRegisterDefs() is constructing.

Evan

On Dec 12, 2007, at 11:59 AM, Evan Cheng wrote:

>
> On Dec 12, 2007, at 9:59 AM, Chris Lattner wrote:
>
>>
>> On Dec 12, 2007, at 1:38 AM, Evan Cheng wrote:
>>
>>>
>>>
>>> On Dec 11, 2007, at 11:40 AM, Bill Wendling <isanbard at gmail.com>
>>> wrote:
>>>
>>>> Author: void
>>>> Date: Tue Dec 11 13:40:06 2007
>>>> New Revision: 44874
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=44874&view=rev
>>>> Log:
>>>> Blark! How in the world did this work without this?!
>>>
>>> One thing that is some what annoying to me is if LICM is after live
>>> variables then it won't need to compute vreg def info or liveness
>>> info. I wonder if it is possible to move the pass after live
>>> variables?
>>
>> What would this give?  liveness for vregs is trivial in ssa form, no?
>
> But not physical registers.
>
> Evan
>
>>
>> -Chris
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