[llvm-commits] [llvm] r44627 - in /llvm/trunk: CREDITS.TXT autoconf/configure.ac lib/Target/CellSPU/SPUCallingConv.td

[Scott Michel]

Author: pingbak
Date: Wed Dec  5 15:23:16 2007
New Revision: 44627

URL: http://llvm.org/viewvc/llvm-project?rev=44627&view=rev
Log:
Minor updates:
- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list

Modified:
    llvm/trunk/CREDITS.TXT
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td

Modified: llvm/trunk/CREDITS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=44627&r1=44626&r2=44627&view=diff

==============================================================================
--- llvm/trunk/CREDITS.TXT (original)
+++ llvm/trunk/CREDITS.TXT Wed Dec  5 15:23:16 2007
@@ -257,3 +257,7 @@
 D: Darwin exception handling
 D: MMX & SSSE3 instructions
 D: SPEC2006 support
+
+N: Scott Michel
+E: scottm at aero.org
+D: Added STI Cell SPU backend.

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=44627&r1=44626&r2=44627&view=diff

==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Wed Dec  5 15:23:16 2007
@@ -363,8 +363,7 @@
     [Build specific host targets: all,host-only,{target-name} (default=all)]),,
     enableval=all)
 case "$enableval" in
-  # Note: Add "CellSPU" to all when fully functional.
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU" ;;
   host-only)
     case "$llvm_cv_target_arch" in
       x86)     TARGETS_TO_BUILD="X86" ;;

Modified: llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td?rev=44627&r1=44626&r2=44627&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td Wed Dec  5 15:23:16 2007
@@ -48,7 +48,6 @@
   // The first 12 Vector arguments are passed in altivec registers.
   CCIfType<[v16i8, v8i16, v4i32, v4f32],
               CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
- */
 /*
   // Integer/FP values get stored in stack slots that are 8 bytes in size and
   // 8-byte aligned if there are no more registers to hold them.
@@ -56,6 +55,6 @@
   
   // Vectors get 16-byte stack slots that are 16-byte aligned.
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
-              CCAssignToStack<16, 16>>
+              CCAssignToStack<16, 16>>*/
 ]>;
  */