[llvm-commits] [llvm] r43776 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

[Evan Cheng]

Author: evancheng
Date: Tue Nov  6 15:12:10 2007
New Revision: 43776

URL: http://llvm.org/viewvc/llvm-project?rev=43776&view=rev
Log:
When the allocator rewrite a spill register with new virtual register, it replaces other operands of the same register. Watch out for situations where
only some of the operands are sub-register uses.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=43776&r1=43775&r2=43776&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Nov  6 15:12:10 2007
@@ -379,10 +379,19 @@
           if (!MI->getOperand(j).isRegister())
             continue;
           unsigned RegJ = MI->getOperand(j).getReg();
-          if (RegJ != 0 && MRegisterInfo::isVirtualRegister(RegJ) &&
-              RegMap->isSubRegister(RegJ))
+          if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ))
+            continue;
+          bool isSubRegJ = RegMap->isSubRegister(RegJ);
+          if (isSubRegJ) {
+            assert(!isSubReg || RegMap->getSubRegisterIndex(RegJ) == SubIdx);
             RegJ = RegMap->getSuperRegister(RegJ);
-          if (RegJ == li.reg) {
+          }
+          // Important to check "isSubRegJ == isSubReg".
+          // e.g. %reg1024 = MOVSX32rr16 %reg1025. It's possible that both
+          // registers are coalesced to the same register but only %reg1025 is
+          // a sub-register use. They should not be rewritten to the same
+          // register.
+          if (RegJ == li.reg && isSubRegJ == isSubReg) {
             MI->getOperand(j).setReg(NewVReg);
             HasUse |= MI->getOperand(j).isUse();
             HasDef |= MI->getOperand(j).isDef();