[llvm-commits] [llvm] r43551 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
Duncan Sands
baldrick at free.fr
Wed Oct 31 01:57:43 PDT 2007
Author: baldrick
Date: Wed Oct 31 03:57:43 2007
New Revision: 43551
URL: http://llvm.org/viewvc/llvm-project?rev=43551&view=rev
Log:
Promotion of sdiv/srem/udiv/urem.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp?rev=43551&r1=43550&r2=43551&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp Wed Oct 31 03:57:43 2007
@@ -147,6 +147,8 @@
SDOperand PromoteResult_SETCC(SDNode *N);
SDOperand PromoteResult_LOAD(LoadSDNode *N);
SDOperand PromoteResult_SimpleIntBinOp(SDNode *N);
+ SDOperand PromoteResult_SDIV(SDNode *N);
+ SDOperand PromoteResult_UDIV(SDNode *N);
SDOperand PromoteResult_SHL(SDNode *N);
SDOperand PromoteResult_SRA(SDNode *N);
SDOperand PromoteResult_SRL(SDNode *N);
@@ -554,6 +556,12 @@
case ISD::SUB:
case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
+ case ISD::SDIV:
+ case ISD::SREM: Result = PromoteResult_SDIV(N); break;
+
+ case ISD::UDIV:
+ case ISD::UREM: Result = PromoteResult_UDIV(N); break;
+
case ISD::SHL: Result = PromoteResult_SHL(N); break;
case ISD::SRA: Result = PromoteResult_SRA(N); break;
case ISD::SRL: Result = PromoteResult_SRL(N); break;
@@ -694,6 +702,30 @@
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
+SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
+ // Sign extend the input.
+ SDOperand LHS = GetPromotedOp(N->getOperand(0));
+ SDOperand RHS = GetPromotedOp(N->getOperand(1));
+ MVT::ValueType VT = N->getValueType(0);
+ LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
+ DAG.getValueType(VT));
+ RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
+ DAG.getValueType(VT));
+
+ return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
+}
+
+SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
+ // Zero extend the input.
+ SDOperand LHS = GetPromotedOp(N->getOperand(0));
+ SDOperand RHS = GetPromotedOp(N->getOperand(1));
+ MVT::ValueType VT = N->getValueType(0);
+ LHS = DAG.getZeroExtendInReg(LHS, VT);
+ RHS = DAG.getZeroExtendInReg(RHS, VT);
+
+ return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
+}
+
SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
GetPromotedOp(N->getOperand(0)), N->getOperand(1));
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