[llvm-commits] [llvm] r43338 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

[Duncan Sands]

Author: baldrick
Date: Thu Oct 25 07:28:12 2007
New Revision: 43338

URL: http://llvm.org/viewvc/llvm-project?rev=43338&view=rev
Log:
Fix comment typos.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=43338&r1=43337&r2=43338&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Oct 25 07:28:12 2007
@@ -235,7 +235,7 @@
     ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
 
     // SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
-    // a signed/unsigned value of type i[2*n], and return the full value as
+    // a signed/unsigned value of type i[2*N], and return the full value as
     // two results, each of type iN.
     SMUL_LOHI, UMUL_LOHI,
 
@@ -319,7 +319,7 @@
     INSERT_SUBREG,
     
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
-    // an unsigned/signed value of type i[2*n], then return the top part.
+    // an unsigned/signed value of type i[2*N], then return the top part.
     MULHU, MULHS,
 
     // Bitwise operators - logical and, logical or, logical xor, shift left,