[llvm-commits] [llvm] r43171 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp

[Duncan Sands]

Hi Chris,

> Assuming an expansion from i64 to 2x i32, the code above will work  
> for sextinreg amounts between 1 and 32.  For greater amounts, the top  
> part should get a sextinreg, and the bottom part should or togther  
> the top and bottom shifted parts, similar to a expanded shift.

not sure why you need to do something complicated for the bottom part.  Consider
sextinreg from i63 to i64.  The operand expands to 2 x i32: Lo and Hi.  It seems
to me that nothing needs to be done to Lo, while Hi needs to undergo an sextinreg
from i31 to i32.

Ciao,

Duncan.