[llvm-commits] [llvm] r43153 - in /llvm/trunk: include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/
Evan Cheng
evan.cheng at apple.com
Thu Oct 18 15:40:57 PDT 2007
Author: evancheng
Date: Thu Oct 18 17:40:57 2007
New Revision: 43153
URL: http://llvm.org/viewvc/llvm-project?rev=43153&view=rev
Log:
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
Modified:
llvm/trunk/include/llvm/Target/MRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h
llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp
llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
Modified: llvm/trunk/include/llvm/Target/MRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/MRegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/MRegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -508,7 +508,7 @@
const TargetRegisterClass *RC) const = 0;
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
@@ -518,7 +518,7 @@
const TargetRegisterClass *RC) const = 0;
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
@@ -577,6 +577,14 @@
return false;
}
+ /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
+ /// instruction after load / store are unfolded from the specified opcode.
+ /// It returns zero if the specified unfolding is impossible.
+ virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
+ bool UnfoldLoad, bool UnfoldStore) const {
+ return 0;
+ }
+
/// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue
/// time).
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -183,7 +183,7 @@
}
void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
@@ -239,7 +239,7 @@
}
void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -52,7 +52,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -62,7 +62,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -83,7 +83,7 @@
}
void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
@@ -128,7 +128,7 @@
}
void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -34,7 +34,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -44,7 +44,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -61,7 +61,7 @@
}
void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
@@ -113,7 +113,7 @@
}
void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -35,7 +35,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -45,7 +45,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -96,7 +96,7 @@
}
void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (RC != Mips::CPURegsRegisterClass)
@@ -128,7 +128,7 @@
}
void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (RC != Mips::CPURegsRegisterClass)
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -38,7 +38,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -48,7 +48,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -182,7 +182,7 @@
}
void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (Addr[0].isFrameIndex()) {
@@ -291,7 +291,7 @@
}
void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (Addr[0].isFrameIndex()) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -41,7 +41,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -51,7 +51,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -49,7 +49,7 @@
}
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
@@ -91,7 +91,7 @@
}
void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -36,7 +36,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -46,7 +46,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Oct 18 17:40:57 2007
@@ -806,7 +806,7 @@
}
void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = getStoreRegOpcode(RC);
@@ -862,7 +862,7 @@
}
void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = getLoadRegOpcode(RC);
@@ -1273,6 +1273,20 @@
return true;
}
+unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
+ bool UnfoldLoad, bool UnfoldStore) const {
+ DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
+ MemOp2RegOpTable.find((unsigned*)Opc);
+ if (I == MemOp2RegOpTable.end())
+ return 0;
+ bool HasLoad = I->second.second & (1 << 4);
+ bool HasStore = I->second.second & (1 << 5);
+ if (UnfoldLoad && !HasLoad)
+ return 0;
+ if (UnfoldStore && !HasStore)
+ return 0;
+ return I->second.first;
+}
const unsigned *
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=43153&r1=43152&r2=43153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Thu Oct 18 17:40:57 2007
@@ -89,7 +89,7 @@
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -99,7 +99,7 @@
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> Addr,
+ SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
@@ -142,6 +142,12 @@
bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
SmallVectorImpl<SDNode*> &NewNodes) const;
+ /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
+ /// instruction after load / store are unfolded from the specified opcode.
+ /// It returns zero if the specified unfolding is impossible.
+ unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
+ bool UnfoldLoad, bool UnfoldStore) const;
+
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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