[llvm-commits] [llvm] r43116 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Chris Lattner]

Author: lattner
Date: Thu Oct 18 01:17:07 2007
New Revision: 43116

URL: http://llvm.org/viewvc/llvm-project?rev=43116&view=rev
Log:
legalizing the ret operation on f64 shouldn't introduce a new
i64 bit convert needlessly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=43116&r1=43115&r2=43116&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Oct 18 01:17:07 2007
@@ -670,10 +670,12 @@
     if (Op.getValueType() == MVT::f32) {
       Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
     } else if (Op.getValueType() == MVT::f64) {
-      // Recursively legalize f64 -> i64.
-      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
-      return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
-                         DAG.getConstant(0, MVT::i32));
+      // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
+      // available.
+      Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
+      SDOperand Sign = DAG.getConstant(0, MVT::i32);
+      return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 
+                         Op.getValue(1), Sign);
     }
     Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
     if (DAG.getMachineFunction().liveout_empty())