[llvm-commits] [llvm] r43068 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Author: lattner
Date: Wed Oct 17 01:17:29 2007
New Revision: 43068

URL: http://llvm.org/viewvc/llvm-project?rev=43068&view=rev
Log:
Change fp to sint legalization on x86-32 to do 2 x i32 
loads instead of 1 x i64 loads.  This doesn't change any functionality yet.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=43068&r1=43067&r2=43068&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Oct 17 01:17:29 2007
@@ -3952,8 +3952,18 @@
   SDOperand Ops[] = { Chain, Value, StackSlot };
   SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
 
-  // Load the result.
-  return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
+  // Load the result.  If this is an i64 load on an x86-32 host, expand the
+  // load.
+  if (Op.getValueType() != MVT::i64 || Subtarget->is64Bit())
+    return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
+  
+  SDOperand Lo = DAG.getLoad(MVT::i32, FIST, StackSlot, NULL, 0);
+  StackSlot = DAG.getNode(ISD::ADD, StackSlot.getValueType(), StackSlot,
+                          DAG.getConstant(StackSlot.getValueType(), 4));
+  SDOperand Hi = DAG.getLoad(MVT::i32, FIST, StackSlot, NULL, 0);
+  
+  
+  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
 }
 
 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {