[llvm-commits] [llvm] r42822 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h lib/Target/PowerPC/PPCInstrFormats.td lib/Target/PowerPC/PPCInstrInfo.td

[Evan Cheng]

On Oct 9, 2007, at 6:01 PM, Dale Johannesen wrote:

>
> ====================================================================== 
> ========
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Oct  9  
> 20:01:31 2007
> @@ -403,6 +403,8 @@
>    SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
>                          const SDOperand *Ops, unsigned NumOps);
>    SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
> +                        MVT::ValueType VT2);
> +  SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
>                          MVT::ValueType VT2, SDOperand Op1);

This seems unnecessary. You can use this variant:
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                         MVT::ValueType VT2,
                         const SDOperand *Ops, unsigned NumOps);
>
> +// Instructions to manipulate FPSCR.  Only long double handling  
> uses these.
> +// FPSCR is not modelled; we use the SDNode Flag to keep things in  
> order.
> +
> +def MFFS   : XForm_42<63, 583, (outs F8RC:$rT), (ins),
> +                       "mffs $rT", IntMFFS,
> +                       [(set F8RC:$rT, (PPCmffs))]>,
> +             PPC970_DGroup_Single, PPC970_Unit_FPU;
> +def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
> +                       "mtfsb0 $FM", IntMTFSB0,
> +                      [(PPCmtfsb0 (i32 imm:$FM))]>,
> +             PPC970_DGroup_Single, PPC970_Unit_FPU;
> +def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
> +                       "mtfsb1 $FM", IntMTFSB0,
> +                      [(PPCmtfsb1 (i32 imm:$FM))]>,
> +             PPC970_DGroup_Single, PPC970_Unit_FPU;
> +def FADDrtz: AForm_2<63, 21,
> +                    (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
> +                    "fadd $FRT, $FRA, $FRB", FPGeneral,
> +                    [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC: 
> $FRB))]>,
> +             PPC970_DGroup_Single, PPC970_Unit_FPU;
> +// MTFSF does not actually produce an FP result.  We pretend it  
> copies
> +// input reg B to the output.  If we didn't do this it would look  
> like the
> +// instruction had no outputs (because we aren't modelling the  
> FPSCR) and
> +// it would be deleted.
> +def MTFSF  : XFLForm<63, 711, (outs F8RC:$FRA),
> +                              (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
> +                       "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
> +                       [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
> +                                                   F8RC:$rT, F8RC: 
> $FRB))]>,
> +             PPC970_DGroup_Single, PPC970_Unit_FPU;

Ewww. :-) It just occurred to me you might want to implement this lot  
with the usesCustomDAGSchedInserter = 1 hack. It allows you to expand  
a pseudo PPC FP_ROUND_INREG node into multiple MI's at the end of  
scheduling. It's also a hack but might be a little bit cleaner than  
this. Sorry it didn't come to me when we were talking about this. :-(

Evan


> +
>  let PPC970_Unit = 1 in {  // FXU Operations.
>
>  // XO-Form instructions.  Arithmetic instructions that can set  
> overflow bit
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits