[llvm-commits] [llvm] r42622 - in /llvm/trunk/lib/Target/IA64: IA64RegisterInfo.cpp IA64RegisterInfo.h

[Evan Cheng]

Author: evancheng
Date: Thu Oct  4 20:33:45 2007
New Revision: 42622

URL: http://llvm.org/viewvc/llvm-project?rev=42622&view=rev
Log:
Forgot these.

Modified:
    llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp
    llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h

Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp?rev=42622&r1=42621&r2=42622&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp Thu Oct  4 20:33:45 2007
@@ -60,6 +60,38 @@
       "sorry, I don't know how to store this sort of reg in the stack\n");
 }
 
+void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+                                      SmallVector<MachineOperand,4> Addr,
+                                      const TargetRegisterClass *RC,
+                                  SmallVector<MachineInstr*, 4> &NewMIs) const {
+  unsigned Opc = 0;
+  if (RC == IA64::FPRegisterClass) {
+    Opc = IA64::STF8;
+  } else if (RC == IA64::GRRegisterClass) {
+    Opc = IA64::ST8;
+  } else if (RC == IA64::PRRegisterClass) {
+    Opc = IA64::ST1;
+  } else {
+    assert(0 &&
+      "sorry, I don't know how to store this sort of reg\n");
+  }
+
+  MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
+  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+    MachineOperand &MO = Addr[i];
+    if (MO.isRegister())
+      MIB.addReg(MO.getReg());
+    else if (MO.isImmediate())
+      MIB.addImm(MO.getImmedValue());
+    else
+      MIB.addFrameIndex(MO.getFrameIndex());
+  }
+  MIB.addReg(SrcReg, false, false, true);
+  NewMIs.push_back(MIB);
+  return;
+
+}
+
 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                             MachineBasicBlock::iterator MI,
                                             unsigned DestReg, int FrameIdx,
@@ -80,6 +112,36 @@
      "sorry, I don't know how to load this sort of reg from the stack\n");
 }
 
+void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                                       SmallVector<MachineOperand,4> Addr,
+                                       const TargetRegisterClass *RC,
+                                       SmallVector<MachineInstr*, 4> &NewMIs) const {
+  unsigned Opc = 0;
+  if (RC == IA64::FPRegisterClass) {
+    Opc = IA64::LDF8;
+  } else if (RC == IA64::GRRegisterClass) {
+    Opc = IA64::LD8;
+  } else if (RC == IA64::PRRegisterClass) {
+    Opc = IA64::LD1;
+  } else {
+    assert(0 &&
+      "sorry, I don't know how to store this sort of reg\n");
+  }
+
+  MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
+  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+    MachineOperand &MO = Addr[i];
+    if (MO.isRegister())
+      MIB.addReg(MO.getReg());
+    else if (MO.isImmediate())
+      MIB.addImm(MO.getImmedValue());
+    else
+      MIB.addFrameIndex(MO.getFrameIndex());
+  }
+  NewMIs.push_back(MIB);
+  return;
+}
+
 void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,

Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h?rev=42622&r1=42621&r2=42622&view=diff

==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h Thu Oct  4 20:33:45 2007
@@ -34,11 +34,21 @@
                            unsigned SrcReg, int FrameIndex,
                            const TargetRegisterClass *RC) const;
 
+  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+                      SmallVector<MachineOperand,4> Addr,
+                      const TargetRegisterClass *RC,
+                      SmallVector<MachineInstr*, 4> &NewMIs) const;
+
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             unsigned DestReg, int FrameIndex,
                             const TargetRegisterClass *RC) const;
 
+  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                       SmallVector<MachineOperand,4> Addr,
+                       const TargetRegisterClass *RC,
+                       SmallVector<MachineInstr*, 4> &NewMIs) const;
+
   void copyRegToReg(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,
                     unsigned DestReg, unsigned SrcReg,