[llvm-commits] [llvm] r42308 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/divrem.ll

[Chris Lattner]

> URL: http://llvm.org/viewvc/llvm-project?rev=42308&view=rev
> Log:
> When both x/y and x%y are needed (x and y both scalar integer),  
> compute
> both results with a single div or idiv instruction. This uses new  
> X86ISD
> nodes for DIV and IDIV which are introduced during the legalize phase
> so that the SelectionDAG's CSE can automatically eliminate redundant
> computations.

Very nice.  Would it make sense to make this be a target independent  
node?  It seems like other chips have similar divide instructions,  
though I can't recall any off-hand.  This would also help with the  
standard problem of target-specific nodes blocking the target- 
independent dag combiner.


If you're interested in this area, another big potential win is for  
long multiplies.  The ARM backend currently has these two target- 
specific nodes:

       MULHILOU,     // Lo,Hi = umul LHS, RHS.
       MULHILOS,     // Lo,Hi = smul LHS, RHS.

It has been on my todo list forever to merge these (and the logic in  
ARMISelLowering.cpp:LowerMUL) up to target-independent code.  This  
would allow the X86 backend to use it, getting better wide multiplies.

-Chris