[llvm-commits] [llvm] r41897 - in /llvm/trunk: lib/Target/TargetSelectionDAG.td utils/TableGen/DAGISelEmitter.cpp utils/TableGen/DAGISelEmitter.h

[Evan Cheng]

On Sep 12, 2007, at 6:00 PM, Chris Lattner wrote:

>> Initial support for multi-result patterns:
>> 1.
>> [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
>> (modify EFLAGS)]
>> This indicates the source pattern expects the instruction would
>> produce 2 values. The first is the result of the addition. The
>> second is an implicit definition in register EFLAGS.
>
> Nice!
>
>> 2.
>> def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify
>> EFLAGS)), ()>
>> Similar to #1 except this is used for def : Pat patterns.
>
> Do we really need this?  Pat is just defined as:
>
> // Pat - A simple (but common) form of a pattern, which produces a
> simple result
> // not needing a full list.
> class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
>
> I would be straight-forward to define a version that took a list
> explicitly.

Ok. I'll play with this a bit more. This is not currently used.


>  Also, what does it mean to match on a modify of EFLAGS?

This is fairly restricted right now. It means the matched instruction  
must implicitly define EFLAGS register and it is being modeled as an  
explicit value produced by the node. For the bogus example listed  
before, it's selected to a ADD32rr that produces 2 values. The  
scheduler will automatically convert the second value into a copy from  
EFLAGS (details still being worked out).

Evan

>
>
> -Chris
>
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