[llvm-commits] [llvm] r41812 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Evan Cheng]

Author: evancheng
Date: Mon Sep 10 17:22:23 2007
New Revision: 41812

URL: http://llvm.org/viewvc/llvm-project?rev=41812&view=rev
Log:
80 col.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=41812&r1=41811&r2=41812&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep 10 17:22:23 2007
@@ -418,8 +418,9 @@
 }
 
 // Almost all ARM instructions are predicable.
-class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-        Format f, string opc, string asm, string cstr, list<dag> pattern>
+class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+        IndexMode im, Format f, string opc, string asm, string cstr,
+        list<dag> pattern>
   : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p));
@@ -431,8 +432,9 @@
 // Same as I except it can optionally modify CPSR. Note it's modeled as
 // an input operand since by default it's a zero register. It will
 // become an implicit def once it's "flipped".
-class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-         Format f, string opc, string asm, string cstr, list<dag> pattern>
+class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+         IndexMode im, Format f, string opc, string asm, string cstr,
+         list<dag> pattern>
   : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));