[llvm-commits] [llvm] r41802 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

Evan Cheng evan.cheng at apple.com
Mon Sep 10 13:48:54 PDT 2007


Author: evancheng
Date: Mon Sep 10 15:48:53 2007
New Revision: 41802

URL: http://llvm.org/viewvc/llvm-project?rev=41802&view=rev
Log:
It's not safe to rematerialize MOV32r0 etc. by simply cloning the original
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=41802&r1=41801&r2=41802&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Sep 10 15:48:53 2007
@@ -265,9 +265,28 @@
                                     MachineBasicBlock::iterator I,
                                     unsigned DestReg,
                                     const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
+  // MOV32r0 etc. are implemented with xor which clobbers condition code.
+  // Re-materialize them as movri instructions to avoid side effects.
+  switch (Orig->getOpcode()) {
+  case X86::MOV8r0:
+    BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
+    break;
+  case X86::MOV16r0:
+    BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
+    break;
+  case X86::MOV32r0:
+    BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
+    break;
+  case X86::MOV64r0:
+    BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
+    break;
+  default: {
+    MachineInstr *MI = Orig->clone();
+    MI->getOperand(0).setReg(DestReg);
+    MBB.insert(I, MI);
+    break;
+  }
+  }
 }
 
 static const MachineInstrBuilder &FuseInstrAddOperand(MachineInstrBuilder &MIB,





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