[llvm-commits] [llvm] r41179 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/X86/X86ISelLowering.cpp

[Rafael Espindola]

Author: rafael
Date: Mon Aug 20 10:18:24 2007
New Revision: 41179

URL: http://llvm.org/viewvc/llvm-project?rev=41179&view=rev
Log:
Partial implementation of calling functions with byval arguments:
 *) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=41179&r1=41178&r2=41179&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Aug 20 10:18:24 2007
@@ -841,9 +841,10 @@
     bool isInReg;
     bool isSRet;
     bool isNest;
+    bool isByVal;
 
     ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
-      isSRet(false), isNest(false) { };
+      isSRet(false), isNest(false), isByVal(false) { };
   };
   typedef std::vector<ArgListEntry> ArgListTy;
   virtual std::pair<SDOperand, SDOperand>

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=41179&r1=41178&r2=41179&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Aug 20 10:18:24 2007
@@ -2905,6 +2905,7 @@
     Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg);
     Entry.isSRet  = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet);
     Entry.isNest  = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest);
+    Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal);
     Args.push_back(Entry);
   }
 
@@ -3967,6 +3968,15 @@
       Flags |= ISD::ParamFlags::InReg;
     if (Args[i].isSRet)
       Flags |= ISD::ParamFlags::StructReturn;
+    if (Args[i].isByVal) {
+      Flags |= ISD::ParamFlags::ByVal;
+      const PointerType *Ty = cast<PointerType>(Args[i].Ty);
+      const StructType *STy = cast<StructType>(Ty->getElementType());
+      unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy));
+      unsigned StructSize  = getTargetData()->getTypeSize(STy);
+      Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
+      Flags |= (StructSize  << ISD::ParamFlags::ByValSizeOffs);
+    }
     if (Args[i].isNest)
       Flags |= ISD::ParamFlags::Nest;
     Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=41179&r1=41178&r2=41179&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 20 10:18:24 2007
@@ -1378,7 +1378,27 @@
         StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
       SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
       PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
-      MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+
+      SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
+      unsigned Flags    = cast<ConstantSDNode>(FlagsOp)->getValue();
+      if (Flags & ISD::ParamFlags::ByVal) {
+        unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
+                               ISD::ParamFlags::ByValAlignOffs);
+        unsigned  Size = (Flags & ISD::ParamFlags::ByValSize) >>
+            ISD::ParamFlags::ByValSizeOffs;
+
+        SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
+        SDOperand  SizeNode = DAG.getConstant(Size, MVT::i32);
+
+        assert(0 && "Not Implemented");
+
+        SDOperand Copy = DAG.getNode(ISD::MEMCPY, MVT::Other, Chain, PtrOff,
+                                     Arg, SizeNode, AlignNode);
+        MemOpChains.push_back(Copy);
+      }
+      else {
+        MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+      }
     }
   }