[llvm-commits] [llvm] r40970 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td

[Evan Cheng]

Author: evancheng
Date: Thu Aug  9 13:05:17 2007
New Revision: 40970

URL: http://llvm.org/viewvc/llvm-project?rev=40970&view=rev
Log:
GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=40970&r1=40969&r2=40970&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Aug  9 13:05:17 2007
@@ -417,13 +417,14 @@
 }
 
 
-// GR16, GR32 subclasses which contain registers that have R8 sub-registers.
+// GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
 // These should only be used for 32-bit mode.
+def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL, AH, CH, DH, BH]>;
 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
-  let SubRegClassList = [GR8];
+  let SubRegClassList = [GR8_];
 }
 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
-  let SubRegClassList = [GR8, GR16];
+  let SubRegClassList = [GR8_, GR16_];
 }
 
 // Scalar SSE2 floating point registers.