[llvm-commits] [llvm] r40520 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Christopher Lamb]

On Jul 26, 2007, at 10:28 PM, Evan Cheng wrote:

> I don't think they are target opcodes.

Is that a suggestion? In the implementation they are:

--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jul 26  
02:48:21 2007
@@ -177,7 +177,9 @@
    enum {
      PHI = 0,
      INLINEASM = 1,
-    LABEL = 2
+    LABEL = 2,
+    EXTRACT_SUBREG = 3,
+    INSERT_SUBREG = 4
    };

> These are similar to phi, copyfromreg, etc.

Not quite. The copyfrom/to reg and inlineasm nodes are ISD DAG nodes  
and are actually ISel'd in ScheduleDAG to the TargetInstrInfo types.

> Target opcodes are those that are target specific, I.e. not shared  
> between targets.

They're part of the low instruction numbers for all targets.
--
Chris

> On Jul 26, 2007, at 8:36 PM, Christopher Lamb  
> <christopher.lamb at gmail.com> wrote:
>
>>
>> On Jul 26, 2007, at 6:27 PM, Evan Cheng wrote:
>>
>>>
>>> On Jul 26, 2007, at 1:12 AM, Christopher Lamb wrote:
>>>
>>>>  /// EmitNode - Generate machine code for an node and needed  
>>>> dependencies.
>>>>  ///
>>>>  void ScheduleDAG::EmitNode(SDNode *Node,
>>>> @@ -436,6 +578,14 @@
>>>>    // If machine instruction
>>>>    if (Node->isTargetOpcode()) {
>>>>      unsigned Opc = Node->getTargetOpcode();
>>>> +
>>>> +    // Handle subreg insert/extract specially
>>>> +    if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
>>>> +        Opc == TargetInstrInfo::INSERT_SUBREG) {
>>>> +      EmitSubregNode(Node, VRBaseMap);
>>>> +      return;
>>>> +    }
>>>> +
>>>
>>> Hi Chris,
>>>
>>> Is this right? EXTRACT_SUBREG and INSERT_SUBREG are not target  
>>> opcodes.
>>
>> Actually, they are both DAG nodes and target opcodes. ISel lowers  
>> the DAG nodes to target opcodes before schedule DAG sees them.
>> --
>> Christopher Lamb
>>
>>
>>
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--
Christopher Lamb



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