[llvm-commits] [llvm] r40519 - in /llvm/trunk: include/llvm/Target/MRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp
Christopher Lamb
christopher.lamb at gmail.com
Thu Jul 26 01:02:00 PDT 2007
Author: clamb
Date: Thu Jul 26 03:01:58 2007
New Revision: 40519
URL: http://llvm.org/viewvc/llvm-project?rev=40519&view=rev
Log:
Have register info provide the inverse mapping of register->superregisters. PR1350
Modified:
llvm/trunk/include/llvm/Target/MRegisterInfo.h
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/MRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/MRegisterInfo.h?rev=40519&r1=40518&r2=40519&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/MRegisterInfo.h Thu Jul 26 03:01:58 2007
@@ -68,6 +68,7 @@
const sc_iterator SubClasses;
const sc_iterator SuperClasses;
const sc_iterator SubRegClasses;
+ const sc_iterator SuperRegClasses;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
const iterator RegsBegin, RegsEnd;
public:
@@ -76,9 +77,10 @@
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
+ const TargetRegisterClass * const *superregcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
: ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
- SubRegClasses(subregcs),
+ SubRegClasses(subregcs), SuperRegClasses(superregcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@@ -131,9 +133,9 @@
return I;
}
- /// hasSubRegClass - return true if the specified TargetRegisterClass is a
+ /// hasSubClass - return true if the specified TargetRegisterClass is a
/// sub-register class of this TargetRegisterClass.
- bool hasSubRegClass(const TargetRegisterClass *cs) const {
+ bool hasSubClass(const TargetRegisterClass *cs) const {
for (int i = 0; SubClasses[i] != NULL; ++i)
if (SubClasses[i] == cs)
return true;
@@ -152,9 +154,9 @@
return I;
}
- /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
+ /// hasSuperClass - return true if the specified TargetRegisterClass is a
/// super-register class of this TargetRegisterClass.
- bool hasSuperRegClass(const TargetRegisterClass *cs) const {
+ bool hasSuperClass(const TargetRegisterClass *cs) const {
for (int i = 0; SuperClasses[i] != NULL; ++i)
if (SuperClasses[i] == cs)
return true;
@@ -173,9 +175,9 @@
return I;
}
- /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
+ /// hasSubRegClass - return true if the specified TargetRegisterClass is a
/// class of a sub-register class for this TargetRegisterClass.
- bool hasSubRegForClass(const TargetRegisterClass *cs) const {
+ bool hasSubRegClass(const TargetRegisterClass *cs) const {
for (int i = 0; SubRegClasses[i] != NULL; ++i)
if (SubRegClasses[i] == cs)
return true;
@@ -199,6 +201,7 @@
for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
if (i == SubReg)
return &SubRegClasses[i];
+ assert(0 && "Invalid subregister index for register class");
return NULL;
}
@@ -214,6 +217,18 @@
return I;
}
+ /// superregclasses_begin / superregclasses_end - Loop over all of
+ /// the superregister classes of this register class.
+ sc_iterator superregclasses_begin() const {
+ return SuperRegClasses;
+ }
+
+ sc_iterator superregclasses_end() const {
+ sc_iterator I = SuperRegClasses;
+ while (*I != NULL) ++I;
+ return I;
+ }
+
/// allocation_order_begin/end - These methods define a range of registers
/// which specify the registers in this class that are valid to register
/// allocate, and the preferred order to allocate them in. For example,
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=40519&r1=40518&r2=40519&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Jul 26 03:01:58 2007
@@ -223,9 +223,9 @@
<< RegisterClasses[i].getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap;
+ std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
-
// Emit the sub-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -246,9 +246,18 @@
for (; rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
- if (!Empty) OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ if (!Empty)
+ OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
+
+ std::map<unsigned, std::set<unsigned> >::iterator SCMI =
+ SuperRegClassMap.find(rc2);
+ if (SCMI == SuperRegClassMap.end()) {
+ SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
+ SCMI = SuperRegClassMap.find(rc2);
+ }
+ SCMI->second.insert(rc);
break;
}
}
@@ -262,6 +271,36 @@
OS << "\n };\n\n";
}
+ // Emit the super-register classes for each RegisterClass
+ for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Super-register Classess...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "SuperRegClasses [] = {\n ";
+
+ bool Empty = true;
+ std::map<unsigned, std::set<unsigned> >::iterator I =
+ SuperRegClassMap.find(rc);
+ if (I != SuperRegClassMap.end()) {
+ for (std::set<unsigned>::iterator II = I->second.begin(),
+ EE = I->second.end(); II != EE; ++II) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
+ if (!Empty)
+ OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+ }
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+ }
+
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -343,6 +382,7 @@
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
<< RC.getName() + "SubRegClasses" << ", "
+ << RC.getName() + "SuperRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", " << RC.getName() << ", "
<< RC.getName() << " + " << RC.Elements.size() << ") {}\n";
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