[llvm-commits] [llvm] r40516 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/TargetSelectionDAG.td

[Christopher Lamb]

Author: clamb
Date: Thu Jul 26 02:34:40 2007
New Revision: 40516

URL: http://llvm.org/viewvc/llvm-project?rev=40516&view=rev
Log:
Add selection DAG nodes for subreg insert/extract. PR1350

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/TargetSelectionDAG.td

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=40516&r1=40515&r2=40516&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jul 26 02:34:40 2007
@@ -289,6 +289,15 @@
     /// elements of the vector are undefined.
     SCALAR_TO_VECTOR,
     
+    // EXTRACT_SUBREG - This node is used to extract a sub-register value. 
+    // This node takes a superreg and a constant sub-register index as operands.
+    EXTRACT_SUBREG,
+    
+    // INSERT_SUBREG - This node is used to insert a sub-register value. 
+    // This node takes a superreg, a subreg value, and a constant sub-register
+    // index as operands.
+    INSERT_SUBREG,
+    
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
     // an unsigned/signed value of type i[2*n], then return the top part.
     MULHU, MULHS,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40516&r1=40515&r2=40516&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jul 26 02:34:40 2007
@@ -957,7 +957,23 @@
       AddLegalizedOperand(SDOperand(Node, i), Tmp1);
     }
     return Tmp2;
-        
+   case ISD::EXTRACT_SUBREG: {
+      Tmp1 = LegalizeOp(Node->getOperand(0));
+      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
+      assert(idx && "Operand must be a constant");
+      Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+    }
+    break;
+  case ISD::INSERT_SUBREG: {
+      Tmp1 = LegalizeOp(Node->getOperand(0));
+      Tmp2 = LegalizeOp(Node->getOperand(1));      
+      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
+      assert(idx && "Operand must be a constant");
+      Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+    }
+    break;      
   case ISD::BUILD_VECTOR:
     switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
     default: assert(0 && "This action is not supported yet!");

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=40516&r1=40515&r2=40516&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jul 26 02:34:40 2007
@@ -3455,7 +3455,10 @@
   case ISD::SHL_PARTS:   return "shl_parts";
   case ISD::SRA_PARTS:   return "sra_parts";
   case ISD::SRL_PARTS:   return "srl_parts";
-
+  
+  case ISD::EXTRACT_SUBREG:     return "extract_subreg";
+  case ISD::INSERT_SUBREG:      return "insert_subreg";
+  
   // Conversion operators.
   case ISD::SIGN_EXTEND: return "sign_extend";
   case ISD::ZERO_EXTEND: return "zero_extend";

Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=40516&r1=40515&r2=40516&view=diff

==============================================================================
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Thu Jul 26 02:34:40 2007
@@ -317,6 +317,11 @@
     SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
     SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
+    
+def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG", 
+    SDTypeProfile<1, 2, []>>;
+def insert_subreg : SDNode<"ISD::INSERT_SUBREG", 
+    SDTypeProfile<1, 3, []>>;
 
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.