[llvm-commits] [llvm] r37962 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp

[Evan Cheng]

Author: evancheng
Date: Fri Jul  6 18:23:19 2007
New Revision: 37962

URL: http://llvm.org/viewvc/llvm-project?rev=37962&view=rev
Log:
Incorrect check.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=37962&r1=37961&r2=37962&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Jul  6 18:23:19 2007
@@ -312,8 +312,7 @@
   
   // If there is only one terminator instruction, process it.
   unsigned LastOpc = LastInst->getOpcode();
-  if (I == MBB.begin() ||
-      isPredicated(--I) || !isUnpredicatedTerminator(I)) {
+  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
     if (LastOpc == ARM::B || LastOpc == ARM::tB) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
@@ -332,8 +331,7 @@
   MachineInstr *SecondLastInst = I;
   
   // If there are three terminators, we don't know what sort of block this is.
-  if (SecondLastInst && I != MBB.begin() &&
-      !isPredicated(--I) && isUnpredicatedTerminator(I))
+  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
     return true;
   
   // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.